A80386DX16

A80386DX16 Datasheet

Based Scaled Index Mode with Displacement The contents of an INDEX register are multiplied by a SCALING factor the result is added to the contents of a BASE register and a DISPLACEMENT to form the operand’s offset EXAMPLE MOV EAX LOCALTABLE EDI 4 EBPa80

Part	Datasheet
A80386DX16	A80386DX16 (pdf)

Related Parts	Information
NG80386DX33	NG80386DX33
NG80386DX20	NG80386DX20

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Intel386TM DX MICROPROCESSOR 32-BIT CHMOS MICROPROCESSOR WITH INTEGRATED MEMORY MANAGEMENT Y Flexible 32-Bit Microprocessor 8 16 32-Bit Data Types 8 General Purpose 32-Bit Registers Y Very Large Address Space 4 Gigabyte Physical 64 Terabyte Virtual 4 Gigabyte Maximum Segment Size Y Integrated Memory Management Unit Virtual Memory Support Optional On-Chip Paging 4 Levels of Protection Fully Compatible with 80286 Y Object Code Compatible with All 8086 Family Microprocessors Y Virtual 8086 Mode Allows Running of 8086 Software in a Protected and Paged System Y Hardware Debugging Support Y Optimized for System Performance Pipelined Instruction Execution On-Chip Address Translation Caches 20 25 and 33 MHz Clock 40 50 and 66 Megabytes Sec Bus Bandwidth Y Numerics Support via Intel387TM DX Math Coprocessor Y Complete System Development Support Software C PL M Assembler System Generation Tools Debuggers PSCOPE ICETM-386 Y High Speed CHMOS IV Technology Y 132 Pin Grid Array Package Y 132 Pin Plastic Quad Flat Package See Packaging Specification Order 231369 The Intel386 DX Microprocessor is an entry-level 32-bit microprocessor designed for single-user applications and operating systems such as MS-DOS and Windows The 32-bit registers and data paths support 32-bit addresses and data types The processor addresses up to four gigabytes of physical memory and 64 terabytes 2 46 of virtual memory The integrated memory management and protection architecture includes address translation registers multitasking hardware and a protection mechanism to support operating systems Instruction pipelining on-chip address translation ensure short average instruction execution times and maximum system throughput The Intel386 DX CPU offers new testability and debugging features Testability features include a self-test and direct access to the page translation cache Four new breakpoint registers provide breakpoint traps on code execution or data accesses for powerful debugging of even ROM-based systems Object-code compatibility with all 8086 family members 8086 8088 80186 80188 80286 means the Intel386 DX offers immediate access to the world’s largest microprocessor software base Intel386TM DX Pipelined 32-Bit Microarchitecture Intel386TM DX and Intel387TM DX are Trademarks of Intel Corporation MS-DOS and Windows are Trademarks of MICROSOFT Corporation 231630 49 Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 1995 December 1995 Order Number 231630-011 Intel386TM DX MICROPROCESSOR 32-BIT CHMOS MICROPROCESSOR WITH INTEGRATED MEMORY MANAGEMENT CONTENTS 1 PIN ASSIGNMENT 1 Pin Description Table 2 BASE ARCHITECTURE 2 1 Introduction 2 Register Overview 2 3 Register Descriptions 2 4 Instruction Set 2 5 Addressing Modes 2 6 Data Types 2 7 Memory Organization 2 8 I O Space 2 9 Interrupts 2 10 Reset and Initialization 2 11 Testability 2 12 Debugging Support 3 REAL MODE ARCHITECTURE 3 1 Real Mode Introduction 3 2 Memory Addressing 3 Reserved Locations 3 4 Interrupts 3 5 Shutdown and Halt 4 PROTECTED MODE ARCHITECTURE 4 1 Introduction 4 2 Addressing Mechanism 4 3 Segmentation 4 Protection 4 5 Paging 4 6 Virtual 8086 Environment 5 FUNCTIONAL DATA 5 1 Introduction 5 2 Signal Description 5 2 1 Introduction 5 2 Clock CLK2 5 2 3 Data Bus D0 through D31 5 2 4 Address Bus BEO through BE3 A2 through A31 5 2 5 Bus Cycle Definition Signals W R D C M IO LOCK 5 2 6 Bus Control Signals ADS READY NA BS16 5 2 7 Bus Arbitration Signals HOLD HLDA 5 2 8 Coprocessor Interface Signals PEREQ BUSY ERROR 5 2 9 Interrupt Signals INTR NMI RESET 5 2 10 Signal Summary 8 9 15 18 20 22 23 24 27 28 32 33 34 34 35 36 46 52 56 61 62 63 64 65 66 67 CONTENTS 6 INSTRUCTION SET 6 1 Instruction Encoding and Clock Count Summary 6 2 Instruction Encoding Details 7 DESIGNING FOR ICETM-386 DX EMULATOR USE 8 MECHANICAL DATA 8 1 Introduction 8 2 Package Dimensions and Mounting 8 3 Package Thermal Specification

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Intel386TM DX MICROPROCESSOR 32-BIT CHMOS MICROPROCESSOR WITH INTEGRATED MEMORY MANAGEMENT

Y Flexible 32-Bit Microprocessor 8 16 32-Bit Data Types 8 General Purpose 32-Bit Registers

Y Very Large Address Space 4 Gigabyte Physical 64 Terabyte Virtual 4 Gigabyte Maximum Segment Size

Y Integrated Memory Management Unit Virtual Memory Support Optional On-Chip Paging 4 Levels of Protection Fully Compatible with 80286

Y Object Code Compatible with All 8086 Family Microprocessors

Y Virtual 8086 Mode Allows Running of 8086 Software in a Protected and Paged System

Y Hardware Debugging Support

Y Optimized for System Performance Pipelined Instruction Execution On-Chip Address Translation Caches 20 25 and 33 MHz Clock 40 50 and 66 Megabytes Sec Bus Bandwidth

Y Numerics Support via Intel387TM DX Math Coprocessor

Y Complete System Development Support Software C PL M Assembler System Generation Tools Debuggers PSCOPE ICETM-386

Y High Speed CHMOS IV Technology

Y 132 Pin Grid Array Package

Y 132 Pin Plastic Quad Flat Package

See Packaging Specification Order 231369

The Intel386 DX Microprocessor is an entry-level 32-bit microprocessor designed for single-user applications and operating systems such as MS-DOS and Windows The 32-bit registers and data paths support 32-bit addresses and data types The processor addresses up to four gigabytes of physical memory and 64 terabytes 2 46 of virtual memory The integrated memory management and protection architecture includes address translation registers multitasking hardware and a protection mechanism to support operating systems Instruction pipelining on-chip address translation ensure short average instruction execution times and maximum system throughput

The Intel386 DX CPU offers new testability and debugging features Testability features include a self-test and direct access to the page translation cache Four new breakpoint registers provide breakpoint traps on code execution or data accesses for powerful debugging of even ROM-based systems

Object-code compatibility with all 8086 family members 8086 8088 80186 80188 80286 means the Intel386 DX offers immediate access to the world’s largest microprocessor software base

Intel386TM DX Pipelined 32-Bit Microarchitecture

Intel386TM DX and Intel387TM DX are Trademarks of Intel Corporation MS-DOS and Windows are Trademarks of MICROSOFT Corporation
231630 49

Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata

COPYRIGHT INTEL CORPORATION 1995

December 1995

Order Number 231630-011

Intel386TM DX MICROPROCESSOR
32-BIT CHMOS MICROPROCESSOR

WITH INTEGRATED MEMORY MANAGEMENT

CONTENTS
1 PIN ASSIGNMENT 1 Pin Description Table
2 BASE ARCHITECTURE 2 1 Introduction 2 Register Overview 2 3 Register Descriptions 2 4 Instruction Set 2 5 Addressing Modes 2 6 Data Types 2 7 Memory Organization 2 8 I O Space 2 9 Interrupts 2 10 Reset and Initialization 2 11 Testability 2 12 Debugging Support
3 REAL MODE ARCHITECTURE 3 1 Real Mode Introduction 3 2 Memory Addressing 3 Reserved Locations 3 4 Interrupts 3 5 Shutdown and Halt
4 PROTECTED MODE ARCHITECTURE 4 1 Introduction 4 2 Addressing Mechanism 4 3 Segmentation 4 Protection 4 5 Paging 4 6 Virtual 8086 Environment
5 FUNCTIONAL DATA 5 1 Introduction 5 2 Signal Description 5 2 1 Introduction 5 2 Clock CLK2 5 2 3 Data Bus D0 through D31 5 2 4 Address Bus BEO through BE3 A2 through A31 5 2 5 Bus Cycle Definition Signals W R D C M IO LOCK 5 2 6 Bus Control Signals ADS READY NA BS16 5 2 7 Bus Arbitration Signals HOLD HLDA 5 2 8 Coprocessor Interface Signals PEREQ BUSY ERROR 5 2 9 Interrupt Signals INTR NMI RESET 5 2 10 Signal Summary
8 9 15 18 20 22 23 24 27 28
32 33 34
34 35 36 46 52 56
61 62 63 64 65 66 67

CONTENTS
6 INSTRUCTION SET 6 1 Instruction Encoding and Clock Count Summary 6 2 Instruction Encoding Details
7 DESIGNING FOR ICETM-386 DX EMULATOR USE
8 MECHANICAL DATA 8 1 Introduction 8 2 Package Dimensions and Mounting 8 3 Package Thermal Specification

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Datasheet ID: A80386DX16 638943