SB80L186EB16

SB80L186EB16 Datasheet

This data sheet replaces the following data sheets 270803-004 80C186EB 270885-003 80C188EB 270921-003 80L186EB 270920-003 80L188EB 272311-001 SB80C188EB SB80L188EB 272312-001 SB80C186EB SB80L186EB

Part	Datasheet
SB80L186EB16	SB80L186EB16 (pdf)

Related Parts	Information
S80L186EB16	S80L186EB16

PDF Datasheet Preview
80C186EB/80C188E B AND 80L186EB/80L188EB 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS • Full Static Operation • True CMOS Inputs and Outputs • Integrate d Feature Set • Available in Extended Temperature Low-Power Static CPU Core Two Independent UARTs each with an Integral Baud Rate Generator Two 8-Bit Multiplexed I/ O Ports Programmable Interrupt Controller Range - 40°C to + 85°C • Speed Versions Available 3V 16 MHz 80L186EB16/80L188EB16 13 MHz 80L186EB13/80L188EB13 Three Programmable 16-Bit Timer/Counters Clock Generator Ten Programmable Chip Selects with Integral Wait-State Generator Memory Refresh Control Unit System Level Testing Support ONCE Mode • Direct Addressing Capability to 1 Mbyte Memory and 64 Kbyte I/O • Speed Versions Available 5V 25 MHz 80C186EB25/80C188EB25 20 MHz 80C186EB20/80C188EB20 • Low-Power Operating Modes Mode Freezes CPU Clocks but keeps Peripherals Active Mode Freezes All Internal Clocks • Supports 80C187 Numeric Coprocessor Interface 80C186EB PLCC Only • Available In Quad Flat Pack QFP Plastic Leaded Chip Carrier PLCC Shrink Quad Flat Pack SQFP 13 MHz 80C186EB13/80C188EB13 The 80C186EB is a second generation CHMOS High-Integration microprocessor. It has features that are new to the 80C186 family and include a STATIC CPU core, an enhanced Chip Select decode unit, two independent Serial Channels, I/O ports, and the capability of Idle or Powerdown low power modes. 272433 1 * Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. July, 2004 Order Number 272433-006 COPYRIGHT INTEL CORPORATION, 2004 80C186EB 80C188EB and 80L186EB 80L188EB 16-Bit High-Integration Embedded Processors CONTENTS INTRODUCTION CORE ARCHITECTURE Bus Interface Unit Clock Generator 80C186EC PERIPHERAL ARCHITECTURE Interrupt Control Unit Timer Counter Unit Serial Communications Unit Chip-Select Unit I O Port Unit Refresh Control Unit Power Management Unit 80C187 Interface 80C186EB Only ONCE Test Mode PACKAGE INFORMATION Prefix Identification Pin Descriptions 80C186EB PINOUT PACKAGE THERMAL SPECIFICATIONS ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings CONTENTS Recommended Connections PAGE 23 DC SPECIFICATIONS ICC versus Frequency and Voltage PDTMR Pin Delay Calculation

PDF Datasheet Preview

80C186EB/80C188E B AND 80L186EB/80L188EB
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
• Full Static Operation
• True CMOS Inputs and Outputs
• Integrate d Feature Set
• Available in Extended Temperature

Low-Power Static CPU Core Two Independent UARTs each with
an Integral Baud Rate Generator Two 8-Bit Multiplexed I/ O Ports Programmable Interrupt Controller

Range - 40°C to + 85°C
• Speed Versions Available 3V 16 MHz 80L186EB16/80L188EB16 13 MHz 80L186EB13/80L188EB13

Three Programmable 16-Bit Timer/Counters

Clock Generator Ten Programmable Chip Selects with

Integral Wait-State Generator Memory Refresh Control Unit System Level Testing Support ONCE

Mode
• Direct Addressing Capability to 1 Mbyte Memory and 64 Kbyte I/O
• Speed Versions Available 5V 25 MHz 80C186EB25/80C188EB25 20 MHz 80C186EB20/80C188EB20
• Low-Power Operating Modes Mode Freezes CPU Clocks but keeps Peripherals Active Mode Freezes All Internal Clocks
• Supports 80C187 Numeric Coprocessor Interface 80C186EB PLCC Only
• Available In Quad Flat Pack QFP Plastic Leaded Chip Carrier PLCC Shrink Quad Flat Pack SQFP
13 MHz 80C186EB13/80C188EB13

The 80C186EB is a second generation CHMOS High-Integration microprocessor. It has features that are new to the 80C186 family and include a STATIC CPU core, an enhanced Chip Select decode unit, two independent Serial Channels, I/O ports, and the capability of Idle or Powerdown low power modes.
272433 1
* Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

July, 2004

Order Number 272433-006

COPYRIGHT INTEL CORPORATION, 2004
80C186EB 80C188EB and 80L186EB 80L188EB 16-Bit High-Integration Embedded Processors

CONTENTS

INTRODUCTION

CORE ARCHITECTURE Bus Interface Unit Clock Generator
80C186EC PERIPHERAL ARCHITECTURE

Interrupt Control Unit Timer Counter Unit Serial Communications Unit Chip-Select Unit I O Port Unit Refresh Control Unit Power Management Unit 80C187 Interface 80C186EB Only ONCE Test Mode

PACKAGE INFORMATION Prefix Identification Pin Descriptions
80C186EB PINOUT

PACKAGE THERMAL SPECIFICATIONS

ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings

CONTENTS

Recommended Connections

PAGE 23

DC SPECIFICATIONS

ICC versus Frequency and Voltage

PDTMR Pin Delay Calculation

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Datasheet ID: SB80L186EB16 638929