NG80960JD3V40

NG80960JD3V40 Datasheet

Removed reference to NG80960JC-40, NG80960JC-33, NG80960JS-16, and NG80960JF-16 from Table 4 on page

Part	Datasheet
NG80960JD3V40	NG80960JD3V40 (pdf)

Related Parts	Information
TG80960JC66	TG80960JC66
NG80960JA3V33	NG80960JA3V33
TG80960JS25	TG80960JS25
NG80960JF3V25	NG80960JF3V25
NG80960JA3V25	NG80960JA3V25
GD80960JA25	GD80960JA25
TG80960JA3V25	TG80960JA3V25
NG80960JC50	NG80960JC50
NG80960JC66	NG80960JC66
GD80960JF33	GD80960JF33
NG80960JD3V66	NG80960JD3V66
NG80960JS25	NG80960JS25
NG80960JD3V50	NG80960JD3V50
TG80960JS33	TG80960JS33
NG80960JS33	NG80960JS33

PDF Datasheet Preview
80960JA/JF/JD/JS/JC/JT V Embedded 32-Bit Microprocessor Product Features Datasheet • Code Compatible with all 80960Jx Processors • High-Performance Embedded Architecture One Instruction/Clock Execution Core Clock Rate is 1x the Bus Clock for 80960JA/JF/JS 2x the Bus Clock for 80960JD/JC 3x the Bus Clock for 80960JT Load/Store Programming Model Sixteen 32-Bit Global Registers Sixteen 32-Bit Local Registers 8 sets Nine Addressing Modes User/Supervisor Protection Model • Two-Way Set Associative Instruction Cache 80960JA - 2 Kbyte 80960JF/JD - 4 Kbyte 80960JS/JC/JT - 16 Kbyte Programmable Cache-Locking Mechanism • Direct Mapped Data Cache 80960JA - 1 Kbyte 80960JF/JD - 2 Kbyte 80960JS/JC/JT - 4 Kbyte Write Through Operation • On-Chip Stack Frame Cache Seven Register Sets May Be Saved Automatic Allocation on Call/Return 0-7 Frames Reserved for High-Priority Interrupts • On-Chip Data RAM 1 Kbyte Critical Variable Storage Single-Cycle Access • V Supply Voltage 5 V Tolerant Inputs TTL Compatible Outputs • High Bandwidth Burst Bus 32-Bit Multiplexed Address/Data Programmable Memory Configuration Selectable 8-, 16-, 32-Bit Bus Widths Supports Unaligned Accesses Big or Little Endian Byte Ordering • High-Speed Interrupt Controller 31 Programmable Priorities Eight Maskable Pins plus NMI# Up to 240 Vectors in Expanded Mode • Two On-Chip Timers Independent 32-Bit Counting Clock Prescaling by 1, 2, 4 or 8 Internal Interrupt Sources • Halt Mode for Low Power • IEEE JTAG Boundary Scan Compatibility • Packages 132-Lead Pin Grid Array PGA 132-Lead Plastic Quad Flat Pack PQFP 196-Ball Mini Plastic Ball Grid Array MPBGA Order Number 273159-006 August 2004 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 80960JA/JF/JD/JS/JC/JT V Embedded 32-Bit Microprocessor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel’s website at AlertVIEW, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, CT Connect, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, i386, i486, i960, iCOMP, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Create & Share, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel Play, Intel Play logo, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel Xeon, Intel XScale, IPLink, Itanium, LANDesk, LanRover, MCS, MMX, MMX logo, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, RemoteExpress, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside., The Journey Inside, TokenExpress, Trillium, VoiceBrick, Vtune, and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright Intel Corporation, 2002, 2004 Datasheet Contents Contents 80960Jx 9 80960 Processor Core 10 Burst Bus 11 Timer Unit Priority Interrupt 11 Instruction Set Summary 12 Faults and Low Power Operation 12 Test 12 Memory-Mapped Control Data Types and Memory Addressing Packaging Available Processors and Packages Pin Descriptions 16 Functional Pin Definitions 16 80960Jx 132-Lead PGA Pinout 23 80960Jx 132-Lead PQFP Pinout 27 80960Jx 196-Ball MPBGA Pinout 30 Electrical Specifications 35 Absolute Maximum Ratings 35 Operating Conditions 35 Connection VCC5 Pin Requirements VCCPLL Pin Requirements 37 D.C. Specifications 38 A.C. 42 A.C. Test Conditions and Derating Curves 45 Output Delay or Hold vs. Load TLX vs. AD Bus Load 47 ICC Active vs. Frequency A.C. Timing Waveforms Device 59 80960JS/JC/JT Device Identification 80960JD Device Identification Register 61 80960JA/JF Device Identification Register 62 Thermal Specifications 63 Thermal Management Accessories Heatsinks 68 Bus Functional Waveforms 69 Basic Bus 79 Boundary-Scan Datasheet Contents Figures 1 80960Jx Microprocessor Package Options 7 2 80960Jx Block 10 3 132-Lead Pin Grid Array Top View-Pins Facing 23 4 132-Lead Pin Grid Array Bottom View-Pins Facing Up 24 5 132-Lead PQFP - Top View 27 6 196-Ball Mini Plastic Ball Grid Array Top View-Balls Facing Down 30 7 196-Ball Mini Plastic Ball Grid Array Bottom View-Balls Facing Up 31 8 VCC5 Current-Limiting Resistor 36 9 VCCPLL Lowpass Filter 37 10 A.C. Test 45 11 Output Delay or Hold vs. Load V Signals 46 12 Output Delay or Hold vs. Load 5 V Signals 46 13 Output Delay or Hold vs. Load 47 14 TLX vs. AD Bus Load V Signals 47 15 TLX vs. AD Bus Load 5 V Signals 48 16 TLX vs. AD Bus Load 48 17 ICC Active Power Supply vs. 49 18 80960JA/JF ICC Active Thermal vs. Frequency 49 19 80960JD ICC Active Power Supply vs. Frequency 50 20 80960JD ICC Active Thermal vs. Frequency 50 21 80960JC ICC Active Power Supply vs. Frequency 51 22 80960JC ICC Active Thermal vs. Frequency 51 23 80960JS ICC Active Power Supply vs. Frequency 52 24 80960JS ICC Active Thermal vs. Frequency 52 25 CLKIN 53 26 TOV1 Output Delay Waveform 53 27 TOF Output Float Waveform 54 28 TIS1 and TIH1 Input Setup and Hold Waveform 54 29 TIS2 and TIH2 Input Setup and Hold Waveform 54 30 TIS3 and TIH3 Input Setup and Hold Waveform 55 31 TIS4 and TIH4 Input Setup and Hold Waveform 55 32 TLX, TLXL and TLXA Relative Timings Waveform 56 33 DT/R# and DEN# Timings 56 34 TCK Waveform 57 A 32-bit multiplexed burst bus provides a high-speed interface to system memory and I/O. A full complement of control signals simplifies the connection of the 80960Jx to external components. The user programs physical and logical memory attributes through memory-mapped control registers MMRs , an extension not found on the Kx, Sx or Cx processors. Physical and logical configuration registers enable the processor to operate with all combinations of bus width and data object alignment. The processor supports a homogeneous byte ordering model. This processor integrates two important peripherals a timer unit and an interrupt controller. These and other hardware resources are programmed through memory-mapped control registers, an extension to the familiar i960 processor architecture. The timer unit TU offers two independent 32-bit timers for use as real-time system clocks and general-purpose system timing. These operate in either single-shot or auto-reload mode and may generate interrupts. The interrupt controller unit ICU provides a flexible, low-latency means for requesting interrupts. The ICU provides full programmability of up to 240 interrupt sources into 31 priority levels. The ICU takes advantage of a cached priority table and optional routine caching to minimize interrupt latency. Clock doubling on the 80960JD/JC processors reduces interrupt latency by 40% compared to the 80960JA/JF, and clock tripling on the 80960JT reduces interrupt latency by 20% compared to the 80960JD/JC. Local registers may be dedicated to high-priority interrupts to further reduce latency. Acting independently from the core, the ICU compares the priorities of posted interrupts with the current process priority, off-loading this task from the core. The ICU also supports the integrated timer interrupts. The 80960Jx features a Halt mode designed to support applications where low power consumption is critical. The halt instruction shuts down instruction execution, resulting in a power savings of up to 90 percent. The 80960Jx’s testability features, including ONCE On-Circuit Emulation mode and Boundary Scan JTAG , provide a powerful environment for design debug and fault diagnosis. Datasheet 80960JA/JF/JD/JS/JC/JT V Embedded 32-Bit Microprocessor The program features a wide variety of development tools which support the i960 processor family. Many of these tools are developed by partner companies some are developed by Intel, such as profile-driven optimizing compilers. For more information on these products, contact your local Intel representative. Figure 80960Jx Block Diagram CLKIN PLL, Clocks, Power Mgmt TAP Boundary Scan Controller 8-Set Local Register Cache Multiply Divide Unit 80960JA - 2K 80960JF/JD - 4K 80960JS/JC/JT - 16K 32-bit buses address / data Physical Region Configuration Control 21 Control Unit Address/ Bus Request Queues Instruction Sequencer Constants Control Execution and Address Generation Unit Memory Interface Unit Two 32-Bit Timers Interrupt Programmable Port Interrupt Controller Memory-Mapped Register Interface Global / Local Register File SRC1 SRC2 DEST effective address 32-bit Address 32-bit Data SRC1 SRC2 DEST SRC 1 SRC 2 DES T SRC1 DEST 3 Independent 32-Bit SRC1, SRC2, and DEST Buses Users may configure the 80960Jx’s bus controller to match an application’s fundamental memory organization. Physical bus width is register-programmed for up to eight regions. Byte ordering and data caching are programmed through a group of logical memory templates and a defaults register. The BCU’s features include: • Multiplexed external bus to minimize pin count • 32-, 16-, and 8-bit bus widths to simplify I/O interfaces • External ready control for address-to-data, data-to-data and data-to-next-address wait state types • Support for big or little endian byte ordering to facilitate the porting of existing program code • Unaligned bus accesses performed transparently • Three-deep load/store queue to decouple the bus from the core Upon reset, the 80960Jx conducts an internal self-test. Then, before executing its first instruction, it performs an external bus confidence test by performing a checksum on the first words of the initialization boot record IBR . Timer Unit The timer unit TU contains two independent 32-bit timers that are capable of counting at several clock rates and generating interrupts. Each is programmed by use of the TU registers. These memory-mapped registers are addressable on 32-bit boundaries. The timers have a single-shot mode and auto-reload capabilities for continuous operation. Each timer has an independent interrupt request to the 80960Jx’s interrupt controller. The TU may generate a fault when unauthorized writes from user mode are detected. Clock prescaling is supported. Priority Interrupt Controller A programmable interrupt controller manages up to 240 external sources through an 8-bit external interrupt port. Alternatively, the interrupt inputs may be configured for individual edge- or leveltriggered inputs. The interrupt unit IU also accepts interrupts from the two on-chip timer channels and a single Non-Maskable Interrupt NMI# pin. Interrupts are serviced according to their priority levels relative to the current process priority. Low interrupt latency is critical to many embedded applications. As part of its highly flexible interrupt mechanism, the 80960Jx exploits several techniques to minimize latency: • Interrupt vectors and interrupt handler routines may be reserved on-chip. • Register frames for high-priority interrupt handlers may be cached on-chip. • The interrupt stack may be placed in cacheable memory space. • Interrupt microcode executes at two or three times the bus frequency for the 80960JD/JC and 80960JT, respectively. Datasheet 80960JA/JF/JD/JS/JC/JT V Embedded 32-Bit Microprocessor Instruction Set Summary The 80960Jx adds several new instructions to the i960 processor core architecture. The new instructions are: • Conditional Move • Conditional Add • Conditional Subtract • Byte Swap • Halt • Cache Control • Interrupt Control Table 2 identifies the instructions that the 80960Jx supports. Refer to the Jx Microprocessor Developer’s Manual 272483 for a detailed description of each instruction. Faults and Debugging The 80960Jx employs a comprehensive fault model. The processor responds to faults by making implicit calls to a fault handling routine. Specific information collected for each fault allows the fault handler to diagnose exceptions and recover appropriately. The processor also has built-in debug capabilities. In software, the 80960Jx may be configured to detect as many as seven different trace event types. Alternatively, mark and fmark instructions may generate trace events explicitly in the instruction stream. Hardware breakpoint registers are also available to trap on execution and data addresses. Low Power Operation Intel fabricates the 80960Jx using an advanced sub-micron manufacturing process. The processor’s sub-micron topology provides the circuit density for optimal cache size and high operating speeds while dissipating modest power. The processor also uses dynamic power management to turn off clocks to unused circuits. Users may program the 80960Jx to enter Halt mode for maximum power savings. In Halt mode, the processor core stops completely while the integrated peripherals continue to function, reducing overall power requirements up to 90 percent. Processor execution resumes from internally or externally generated interrupts. Test Features The 80960Jx incorporates numerous features that enhance the user’s ability to test both the processor and the system to which it is attached. These features include ONCE On-Circuit Emulation mode and Boundary Scan JTAG . Datasheet 80960JA/JF/JD/JS/JC/JT V Embedded 32-Bit Microprocessor The 80960Jx provides testability features compatible with IEEE Standard Test Access Port and Boundary Scan Architecture IEEE Std. One of the boundary scan instructions, HIGHZ, forces the processor to float all its output pins ONCE mode . ONCE mode may also be initiated at reset without using the boundary scan mechanism. ONCE mode is useful for board-level testing. This feature allows a mounted 80960Jx to electrically “remove” itself from a circuit board. This allows for system-level testing in which a remote tester, such as an in-circuit emulator, may exercise the processor system. The provided test logic does not interfere with component or circuit board behavior and ensures that components function correctly, connections between various components are correct, and various components interact correctly on the printed circuit board. The JTAG Boundary Scan feature is an attractive alternative to conventional “bed-of-nails” testing. It may examine connections that might otherwise be inaccessible to a test system. Memory-Mapped Control Registers The 80960Jx, although compliant with the i960 processor core, has the added advantage of memory-mapped, internal control registers not found on the i960 Kx, Sx or Cx processors. These registers give software the interface to easily read and modify internal control registers. Each of these registers is accessed as a memory-mapped, 32-bit register. Access is accomplished through regular memory-format instructions. The processor ensures that these accesses do not generate external bus cycles. Data Types and Memory Addressing Modes As with all i960 processors, the 80960Jx instruction set supports several data types and formats: • Bit • Bit fields • Integer 8-, 16-, 32-, 64-bit • Ordinal 8-, 16-, 32-, 64-bit unsigned integers • Triple word 96 bits • Quad word 128 bits The 80960Jx provides a full set of addressing modes for C and assembly programming: • Two Absolute modes • Five Register Indirect modes • Index with displacement • IP with displacement

PDF Datasheet Preview

80960JA/JF/JD/JS/JC/JT V Embedded 32-Bit Microprocessor

Product Features

Datasheet
• Code Compatible with all 80960Jx Processors
• High-Performance Embedded Architecture One Instruction/Clock Execution

Core Clock Rate is 1x the Bus Clock for 80960JA/JF/JS 2x the Bus Clock for 80960JD/JC 3x the Bus Clock for 80960JT

Load/Store Programming Model Sixteen 32-Bit Global Registers

Sixteen 32-Bit Local Registers 8 sets Nine Addressing Modes User/Supervisor Protection Model
• Two-Way Set Associative Instruction Cache 80960JA - 2 Kbyte 80960JF/JD - 4 Kbyte
80960JS/JC/JT - 16 Kbyte Programmable Cache-Locking

Mechanism
• Direct Mapped Data Cache
80960JA - 1 Kbyte
80960JF/JD - 2 Kbyte 80960JS/JC/JT - 4 Kbyte Write Through Operation
• On-Chip Stack Frame Cache Seven Register Sets May Be Saved

Automatic Allocation on Call/Return 0-7 Frames Reserved for High-Priority

Interrupts
• On-Chip Data RAM 1 Kbyte Critical Variable Storage Single-Cycle Access
• V Supply Voltage 5 V Tolerant Inputs TTL Compatible Outputs
• High Bandwidth Burst Bus 32-Bit Multiplexed Address/Data Programmable Memory Configuration Selectable 8-, 16-, 32-Bit Bus Widths Supports Unaligned Accesses Big or Little Endian Byte Ordering
• High-Speed Interrupt Controller 31 Programmable Priorities Eight Maskable Pins plus NMI# Up to 240 Vectors in Expanded Mode
• Two On-Chip Timers Independent 32-Bit Counting Clock Prescaling by 1, 2, 4 or 8 Internal Interrupt Sources
• Halt Mode for Low Power
• IEEE JTAG Boundary Scan

Compatibility
• Packages
132-Lead Pin Grid Array PGA 132-Lead Plastic Quad Flat Pack

PQFP 196-Ball Mini Plastic Ball Grid Array

MPBGA

Order Number 273159-006 August 2004

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 80960JA/JF/JD/JS/JC/JT V Embedded 32-Bit Microprocessor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel’s website at

AlertVIEW, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, CT Connect, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, i386, i486, i960, iCOMP, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Create & Share, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel Play, Intel Play logo, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel Xeon, Intel XScale, IPLink, Itanium, LANDesk, LanRover, MCS, MMX, MMX logo, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, RemoteExpress, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside., The Journey Inside, TokenExpress, Trillium, VoiceBrick, Vtune, and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.

Copyright Intel Corporation, 2002, 2004

Datasheet

Contents

Contents
80960Jx 9
80960 Processor Core 10 Burst Bus 11 Timer Unit Priority Interrupt 11 Instruction Set Summary 12 Faults and Low Power Operation 12 Test 12 Memory-Mapped Control Data Types and Memory Addressing

Packaging

Available Processors and Packages Pin Descriptions 16

Functional Pin Definitions 16 80960Jx 132-Lead PGA Pinout 23 80960Jx 132-Lead PQFP Pinout 27 80960Jx 196-Ball MPBGA Pinout 30

Electrical Specifications 35

Absolute Maximum Ratings 35 Operating Conditions 35 Connection VCC5 Pin Requirements VCCPLL Pin Requirements 37 D.C. Specifications 38 A.C. 42

A.C. Test Conditions and Derating Curves 45 Output Delay or Hold vs. Load TLX vs. AD Bus Load 47 ICC Active vs. Frequency

A.C. Timing Waveforms

Device 59
80960JS/JC/JT Device Identification 80960JD Device Identification Register 61 80960JA/JF Device Identification Register 62

Thermal Specifications 63

Thermal Management Accessories Heatsinks 68

Bus Functional Waveforms 69

Basic Bus 79 Boundary-Scan

Datasheet

Contents

Figures
1 80960Jx Microprocessor Package Options 7
2 80960Jx Block 10
3 132-Lead Pin Grid Array Top View-Pins Facing 23
4 132-Lead Pin Grid Array Bottom View-Pins Facing Up 24
5 132-Lead PQFP - Top View 27
6 196-Ball Mini Plastic Ball Grid Array Top View-Balls Facing Down 30
7 196-Ball Mini Plastic Ball Grid Array Bottom View-Balls Facing Up 31
8 VCC5 Current-Limiting Resistor 36
9 VCCPLL Lowpass Filter 37
10 A.C. Test 45
11 Output Delay or Hold vs. Load V Signals 46
12 Output Delay or Hold vs. Load 5 V Signals 46
13 Output Delay or Hold vs. Load 47
14 TLX vs. AD Bus Load V Signals 47 15 TLX vs. AD Bus Load 5 V Signals 48 16 TLX vs. AD Bus Load 48 17 ICC Active Power Supply vs. 49 18 80960JA/JF ICC Active Thermal vs. Frequency 49 19 80960JD ICC Active Power Supply vs. Frequency 50 20 80960JD ICC Active Thermal vs. Frequency 50 21 80960JC ICC Active Power Supply vs. Frequency 51 22 80960JC ICC Active Thermal vs. Frequency 51 23 80960JS ICC Active Power Supply vs. Frequency 52 24 80960JS ICC Active Thermal vs. Frequency 52 25 CLKIN 53
26 TOV1 Output Delay Waveform 53 27 TOF Output Float Waveform 54 28 TIS1 and TIH1 Input Setup and Hold Waveform 54 29 TIS2 and TIH2 Input Setup and Hold Waveform 54 30 TIS3 and TIH3 Input Setup and Hold Waveform 55 31 TIS4 and TIH4 Input Setup and Hold Waveform 55 32 TLX, TLXL and TLXA Relative Timings Waveform 56 33 DT/R# and DEN# Timings 56
34 TCK Waveform 57
A 32-bit multiplexed burst bus provides a high-speed interface to system memory and I/O. A full complement of control signals simplifies the connection of the 80960Jx to external components. The user programs physical and logical memory attributes through memory-mapped control registers MMRs , an extension not found on the Kx, Sx or Cx processors. Physical and logical configuration registers enable the processor to operate with all combinations of bus width and data object alignment. The processor supports a homogeneous byte ordering model.

This processor integrates two important peripherals a timer unit and an interrupt controller. These and other hardware resources are programmed through memory-mapped control registers, an extension to the familiar i960 processor architecture.

The timer unit TU offers two independent 32-bit timers for use as real-time system clocks and general-purpose system timing. These operate in either single-shot or auto-reload mode and may generate interrupts.

The interrupt controller unit ICU provides a flexible, low-latency means for requesting interrupts. The ICU provides full programmability of up to 240 interrupt sources into 31 priority levels. The ICU takes advantage of a cached priority table and optional routine caching to minimize interrupt latency. Clock doubling on the 80960JD/JC processors reduces interrupt latency by 40% compared to the 80960JA/JF, and clock tripling on the 80960JT reduces interrupt latency by 20% compared to the 80960JD/JC. Local registers may be dedicated to high-priority interrupts to further reduce latency. Acting independently from the core, the ICU compares the priorities of posted interrupts with the current process priority, off-loading this task from the core. The ICU also supports the integrated timer interrupts.

The 80960Jx features a Halt mode designed to support applications where low power consumption is critical. The halt instruction shuts down instruction execution, resulting in a power savings of up to 90 percent.

The 80960Jx’s testability features, including ONCE On-Circuit Emulation mode and Boundary Scan JTAG , provide a powerful environment for design debug and fault diagnosis.

Datasheet
80960JA/JF/JD/JS/JC/JT V Embedded 32-Bit Microprocessor

The program features a wide variety of development tools which support the i960 processor family. Many of these tools are developed by partner companies some are developed by Intel, such as profile-driven optimizing compilers. For more information on these products, contact your local Intel representative.

Figure 80960Jx Block Diagram

CLKIN

PLL, Clocks, Power Mgmt

TAP Boundary Scan

Controller
8-Set Local Register Cache

Multiply Divide

Unit
80960JA - 2K 80960JF/JD - 4K 80960JS/JC/JT - 16K
32-bit buses address / data

Physical Region Configuration

Control 21

Control Unit

Address/

Bus Request

Queues

Instruction Sequencer Constants Control

Execution and

Address Generation

Unit

Memory Interface

Unit

Two 32-Bit Timers

Interrupt

Programmable Port

Interrupt Controller

Memory-Mapped Register Interface

Global / Local Register File SRC1 SRC2 DEST
effective address
32-bit Address 32-bit Data

SRC1 SRC2 DEST SRC 1 SRC 2 DES T SRC1 DEST
3 Independent 32-Bit SRC1, SRC2, and DEST Buses
Users may configure the 80960Jx’s bus controller to match an application’s fundamental memory organization. Physical bus width is register-programmed for up to eight regions. Byte ordering and data caching are programmed through a group of logical memory templates and a defaults register.

The BCU’s features include:
• Multiplexed external bus to minimize pin count
• 32-, 16-, and 8-bit bus widths to simplify I/O interfaces
• External ready control for address-to-data, data-to-data and data-to-next-address wait state
types
• Support for big or little endian byte ordering to facilitate the porting of existing program code
• Unaligned bus accesses performed transparently
• Three-deep load/store queue to decouple the bus from the core

Upon reset, the 80960Jx conducts an internal self-test. Then, before executing its first instruction, it performs an external bus confidence test by performing a checksum on the first words of the initialization boot record IBR .

Timer Unit

The timer unit TU contains two independent 32-bit timers that are capable of counting at several clock rates and generating interrupts. Each is programmed by use of the TU registers. These memory-mapped registers are addressable on 32-bit boundaries. The timers have a single-shot mode and auto-reload capabilities for continuous operation. Each timer has an independent interrupt request to the 80960Jx’s interrupt controller. The TU may generate a fault when unauthorized writes from user mode are detected. Clock prescaling is supported.

Priority Interrupt Controller

A programmable interrupt controller manages up to 240 external sources through an 8-bit external interrupt port. Alternatively, the interrupt inputs may be configured for individual edge- or leveltriggered inputs. The interrupt unit IU also accepts interrupts from the two on-chip timer channels and a single Non-Maskable Interrupt NMI# pin. Interrupts are serviced according to their priority levels relative to the current process priority.

Low interrupt latency is critical to many embedded applications. As part of its highly flexible interrupt mechanism, the 80960Jx exploits several techniques to minimize latency:
• Interrupt vectors and interrupt handler routines may be reserved on-chip.
• Register frames for high-priority interrupt handlers may be cached on-chip.
• The interrupt stack may be placed in cacheable memory space.
• Interrupt microcode executes at two or three times the bus frequency for the 80960JD/JC and
80960JT, respectively.

Datasheet
80960JA/JF/JD/JS/JC/JT V Embedded 32-Bit Microprocessor

Instruction Set Summary

The 80960Jx adds several new instructions to the i960 processor core architecture. The new instructions are:
• Conditional Move
• Conditional Add
• Conditional Subtract
• Byte Swap
• Halt
• Cache Control
• Interrupt Control

Table 2 identifies the instructions that the 80960Jx supports. Refer to the Jx Microprocessor Developer’s Manual 272483 for a detailed description of each instruction.

Faults and Debugging

The 80960Jx employs a comprehensive fault model. The processor responds to faults by making implicit calls to a fault handling routine. Specific information collected for each fault allows the fault handler to diagnose exceptions and recover appropriately.

The processor also has built-in debug capabilities. In software, the 80960Jx may be configured to detect as many as seven different trace event types. Alternatively, mark and fmark instructions may generate trace events explicitly in the instruction stream. Hardware breakpoint registers are also available to trap on execution and data addresses.

Low Power Operation

Intel fabricates the 80960Jx using an advanced sub-micron manufacturing process. The processor’s sub-micron topology provides the circuit density for optimal cache size and high operating speeds while dissipating modest power. The processor also uses dynamic power management to turn off clocks to unused circuits.

Users may program the 80960Jx to enter Halt mode for maximum power savings. In Halt mode, the processor core stops completely while the integrated peripherals continue to function, reducing overall power requirements up to 90 percent. Processor execution resumes from internally or externally generated interrupts.

Test Features

The 80960Jx incorporates numerous features that enhance the user’s ability to test both the processor and the system to which it is attached. These features include ONCE On-Circuit Emulation mode and Boundary Scan JTAG .

Datasheet
80960JA/JF/JD/JS/JC/JT V Embedded 32-Bit Microprocessor

The 80960Jx provides testability features compatible with IEEE Standard Test Access Port and Boundary Scan Architecture IEEE Std.

One of the boundary scan instructions, HIGHZ, forces the processor to float all its output pins ONCE mode . ONCE mode may also be initiated at reset without using the boundary scan mechanism.

ONCE mode is useful for board-level testing. This feature allows a mounted 80960Jx to electrically “remove” itself from a circuit board. This allows for system-level testing in which a remote tester, such as an in-circuit emulator, may exercise the processor system.

The provided test logic does not interfere with component or circuit board behavior and ensures that components function correctly, connections between various components are correct, and various components interact correctly on the printed circuit board.

The JTAG Boundary Scan feature is an attractive alternative to conventional “bed-of-nails” testing. It may examine connections that might otherwise be inaccessible to a test system.

Memory-Mapped Control Registers

The 80960Jx, although compliant with the i960 processor core, has the added advantage of memory-mapped, internal control registers not found on the i960 Kx, Sx or Cx processors. These registers give software the interface to easily read and modify internal control registers.

Each of these registers is accessed as a memory-mapped, 32-bit register. Access is accomplished through regular memory-format instructions. The processor ensures that these accesses do not generate external bus cycles.

Data Types and Memory Addressing Modes

As with all i960 processors, the 80960Jx instruction set supports several data types and formats:
• Bit
• Bit fields
• Integer 8-, 16-, 32-, 64-bit
• Ordinal 8-, 16-, 32-, 64-bit unsigned integers
• Triple word 96 bits
• Quad word 128 bits

The 80960Jx provides a full set of addressing modes for C and assembly programming:
• Two Absolute modes
• Five Register Indirect modes
• Index with displacement
• IP with displacement

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived NG80960JD3V40 Datasheet file may be downloaded here without warranties.

Datasheet ID: NG80960JD3V40 638925