A80960HT75SL2GP

A80960HT75SL2GP Datasheet

• Removed core speed of 32 MHz and bus speed of 16 MHz, and order number A80960HD32-S-L2GG from the 168L PGA package, 80960HD device.

Part	Datasheet
A80960HT75SL2GP	A80960HT75SL2GP (pdf)

Related Parts	Information
FC80960HA40SL2GW	FC80960HA40SL2GW
FC80960HA33SL2GV	FC80960HA33SL2GV
FC80960HT75SL2GT	FC80960HT75SL2GT
A80960HA33SL2GY	A80960HA33SL2GY
FC80960HD80SL2LZ	FC80960HD80SL2LZ
UG80960HD6616SL2GN	UG80960HD6616SL2GN

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80960HA/HD/HT 32-Bit High-Performance Superscalar Processor Product Features Datasheet s 32-Bit Parallel Architecture Load/Store Architecture Sixteen 32-Bit Global Registers Sixteen 32-Bit Local Registers Gbyte Internal Bandwidth 80 MHz On-Chip Register Cache s Processor Core Clock 80960HA is 1x Bus Clock 80960HD is 2x Bus Clock 80960HT is 3x Bus Clock s Binary Compatible with Other 80960 Processors s Issue Up To 150 Million Instructions per Second s High-Performance On-Chip Storage 16 Kbyte Four-Way Set-Associative Instruction Cache 8 Kbyte Four-Way Set-Associative Data Cache 2 Kbyte General Purpose RAM s Separate 128-Bit Internal Paths For Instructions/Data s V Supply Voltage 5 V Tolerant Inputs TTL Compatible Outputs s Guarded Memory Unit Provides Memory Protection User/Supervisor Read/Write/Execute s 32-Bit Demultiplexed Burst Bus Per-Byte Parity Generation/Checking Address Pipelining Option Fully Programmable Wait State Generator Supports 8-, 16- or 32-Bit Bus Widths 160 Mbyte/s External Bandwidth 40 MHz s High-Speed Interrupt Controller Up to 240 External Interrupts 31 Fully Programmable Priorities Separate, Non-maskable Interrupt Pin s Dual On-Chip 32-Bit Timers Auto Reload Capability and One-Shot CLKIN Prescaling, divided by 1, 2, 4 or 8 JTAG Support - IEEE Compliant Order Number 272495-009 August 2004 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel’s website at Copyright Intel Corporation, 2002, 2004 AlertVIEW, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, CT Connect, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, i386, i486, i960, iCOMP, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Create & Share, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel Play, Intel Play logo, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel Xeon, Intel XScale, IPLink, Itanium, LANDesk, LanRover, MCS, MMX, MMX logo, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, RemoteExpress, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside., The Journey Inside, TokenExpress, Trillium, VoiceBrick, Vtune, and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Datasheet Contents Contents About This Document 9 Intel 80960Hx Processor 9 The Processor Family Key 80960Hx Features Execution Architecture Pipelined, Burst Bus On-Chip Caches and Data Priority Interrupt Guarded Memory Unit Dual Programmable Timers Processor Self Test Instruction Set Summary Package Information Pin Descriptions 80960Hx Mechanical 80960Hx PGA 80960Hx PQ4 Pinout Package Thermal Specifications Heat Sink PowerQuad4 Plastic Package Stepping Register Information Sources for Accessories Electrical Specifications Absolute Maximum Ratings Operating Conditions Recommended Connections VCC5 Pin Requirements VDIFF VCCPLL Pin Requirements DC Specifications AC AC Test Conditions AC Timing Waveforms Bus Waveforms 80960Hx Boundary Scan Chain Boundary Scan Description Language Example Figures 1 80960Hx Block Diagram 9 2 80960Hx 168-Pin PGA from Top Pins Facing Down 3 80960Hx 168-Pin PGA from Bottom Pins Facing Up 4 80960Hx 208-Pin PQ4 5 Measuring 80960Hx PGA Case Temperature 6 80960Hx Device Identification Datasheet Contents 7 VCC5 Current-Limiting Resistor 38 8 AC Test 45 9 CLKIN 46 10 Output Delay Waveform 46 11 Output Delay Waveform 46 12 Output Float Waveform 47 13 Input Setup and Hold Waveform 47 14 NMI, XINT7:0 Input Setup and Hold 47 15 Hold Acknowledge Timings 48 16 Bus Backoff BOFF Timings 48 17 TCK Waveform 49 18 Input Setup and Hold Waveforms for TBSIS1 and 49 19 Output Delay and Output Float for TBSOV1 and TBSOF1 50 20 Output Delay and Output Float Waveform for TBSOV2 and TBSOF2 50 21 Input Setup and Hold Waveform for TBSIS2 and TBSIH2 50 22 Rise and Fall Time Derating at 85 °C and Minimum 51 23 ICC Active Power Supply vs. 51 24 ICC Active Thermal vs. 52 25 Output Delay or Hold vs. Load Capacitance 52 26 Output Delay vs. Temperature 53 27 Output Hold Times vs. Temperature 53 28 Output Delay vs. VCC 53 29 Cold Reset Waveform 54 30 Warm Reset Waveform 55 31 Entering ONCE 56 32 Non-Burst, Non-Pipelined Requests without Wait States 57 33 Non-Burst, Non-Pipelined Read Request with Wait States 58 34 Non-Burst, Non-Pipelined Write Request with Wait States 59 35 Burst, Non-Pipelined Read Request without Wait States, 32-Bit Bus 60 36 Burst, Non-Pipelined Read Request with Wait States, 32-Bit Bus 61 37 Burst, Non-Pipelined Write Request without Wait States, 32-Bit Bus 62 38 Burst, Non-Pipelined Write Request with Wait States, 32-Bit Bus 63 39 Burst, Non-Pipelined Read Request with Wait States, 16-Bit Bus 64 40 Burst, Non-Pipelined Read Request with Wait States, 8-Bit Bus 65 41 Non-Burst, Pipelined Read Request without Wait States, 32-Bit Bus 66 42 Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus 67 43 Burst, Pipelined Read Request without Wait States, 32-Bit Bus 68 44 Burst, Pipelined Read Request with Wait States, 32-Bit Bus 69 45 Burst, Pipelined Read Request with Wait States, 8-Bit Bus 70 46 Burst, Pipelined Read Request with Wait States, 16-Bit Bus 71 47 Using External 72 48 Terminating a Burst with BTERM 73 49 BREQ and BSTALL Operation 74 50 BOFF Functional Timing. BOFF occurs during a burst or non-burst data cycle. 75 51 HOLD Functional Timing 76 52 LOCK Delays HOLDA 77 53 FAIL Functional 77 54 A Summary of Aligned and Unaligned Transfers for 32-Bit 78 55 A Summary of Aligned and Unaligned Transfers for 32-Bit Regions Continued 79 56 A Summary of Aligned and Unaligned Transfers for 16-Bit 80 Datasheet Contents 57 A Summary of Aligned and Unaligned Transfers for 8-Bit 58 Idle Bus Operation 59 Bus States Tables 1 80960Hx Product Description 9 2 Fail Codes For BIST bit 7 = 1 3 Remaining Fail Codes bit 7 = 0 4 80960Hx Instruction Set 5 80960HA/HD/HT Package Types and 6 Pin Description Nomenclature 7 80960Hx Processor Family Pin 8 80960Hx 168-Pin PGA Name 9 80960Hx 168-Pin PGA Number Order 10 80960Hx PQ4 Name 11 80960Hx PQ4 Number Order 13 80960Hx 168-Pin PGA Package Thermal Characteristics 12 Maximum TA at Various Airflows in °C PGA Package Only 15 80960Hx 208-Pin PQ4 Package Thermal 14 Maximum TA at Various Airflows in °C PQ4 Package 17 80960Hx Device ID Model Types 18 Device ID Version Numbers for Different 16 Fields of 80960Hx Device ID 19 Absolute Maximum Ratings 20 Operating Conditions 21 VDIFF Specification for Dual Power Supply Requirements V, 5 V 22 80960Hx DC Characteristics 23 80960Hx AC 25 80960Hx Boundary Scan Test Signal Timings 24 AC Characteristics 26 80960Hx Boundary Scan Chain Datasheet Contents History August 2004 To address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x". Formatted the datasheet in a new template. In “32-Bit Parallel Architecture” on page 1: • Removed operating frequency of 16/32 bus/core from 80960HD. • Removed operating frequency of 20/60 bus/core from 80960HT. In Table 5 “80960HA/HD/HT Package Types and Speeds” on page 14: September 2002 • Removed core speed of 32 MHz and bus speed of 16 MHz, and order number A80960HD32-S-L2GG from the 168L PGA package, 80960HD device. In Table 11 “80960Hx PQ4 Number Order” on page 29: In Section “Absolute Maximum Ratings” on page 37: • Added section. In Table 22 “80960Hx DC Characteristics” on page 40: • Added footnote 1 to ILO notes column for TDO pin. • Added footnote 10 to CIN, COUT and CI/O pin. Datasheet Contents July 1998 continued History 007 continued In Table 23 “80960Hx AC Characteristics” on page 42 • Added overbars where required. • Modified TDVNH to list separate specifications for V and 5 V. • Modified TOV2, TOH2 and TTVEL to reflect specific 80960HA, 80960HD and 80960HT values. In Figure 23 “ICC Active Power Supply vs. Frequency” on page 51 • Changed ‘5’ to ‘0’ on the CLKIN Frequency axis. In Figure 49 “BREQ and BSTALL Operation” on page 74 • Added figure and following text. August 1997 Fixed several font and format issues. Datasheet Contents This page intentionally left blank. Datasheet 80960HA/HD/HT About This Document This document describes the parametric performance of Intel’s 80960Hx embedded superscalar microprocessors. Detailed descriptions for functional topics, other than parametric performance, are published in the Hx Microprocessor User’s Guide In this document, ‘80960Hx’ and ‘i960 Hx processor’ refer to the products described in Table Throughout this document, information that is specific to each is clearly indicated. Figure 80960Hx Block Diagram JTAG Port Timers Interrupt Programmable Port Interrupt Controller Multiply/Divide Unit Execution Unit Instruction Prefetch Queue Instruction Cache 16 Kbyte, Four-Way Set-Associative 128-Bit Cache Bus Parallel Instruction Scheduler Register-Side Memory-Side Machine Bus Machine Bus Six-Port Register File 64-bit SRC1 Bus 32-bit Base Bus 64-bit SRC2 Bus 128-bit Load Bus 64-bit DST Bus 128-bit Store Bus Guarded Memory Unit Control Memory Region Configuration Bus Controller Address Bus Request Queues Data Data Cache 8 Kbyte, Four-Way Set-Associative Data RAM - 2 Kbyte Register Cache - 5 to 15 sets

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80960HA/HD/HT 32-Bit High-Performance Superscalar Processor

Product Features

Datasheet
s 32-Bit Parallel Architecture Load/Store Architecture

Sixteen 32-Bit Global Registers

Sixteen 32-Bit Local Registers

Gbyte Internal Bandwidth 80 MHz

On-Chip Register Cache
s Processor Core Clock 80960HA is 1x Bus Clock
80960HD is 2x Bus Clock
80960HT is 3x Bus Clock
s Binary Compatible with Other 80960 Processors
s Issue Up To 150 Million Instructions per Second
s High-Performance On-Chip Storage 16 Kbyte Four-Way Set-Associative Instruction Cache
8 Kbyte Four-Way Set-Associative Data Cache
2 Kbyte General Purpose RAM
s Separate 128-Bit Internal Paths For Instructions/Data
s V Supply Voltage 5 V Tolerant Inputs TTL Compatible Outputs
s Guarded Memory Unit Provides Memory Protection User/Supervisor Read/Write/Execute
s 32-Bit Demultiplexed Burst Bus Per-Byte Parity Generation/Checking Address Pipelining Option Fully Programmable Wait State Generator Supports 8-, 16- or 32-Bit Bus Widths 160 Mbyte/s External Bandwidth 40 MHz
s High-Speed Interrupt Controller Up to 240 External Interrupts 31 Fully Programmable Priorities Separate, Non-maskable Interrupt Pin
s Dual On-Chip 32-Bit Timers Auto Reload Capability and One-Shot CLKIN Prescaling, divided by 1, 2, 4 or 8 JTAG Support - IEEE Compliant

Order Number 272495-009 August 2004

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel’s website at

Copyright Intel Corporation, 2002, 2004

AlertVIEW, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, CT Connect, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, i386, i486, i960, iCOMP, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Create & Share, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel Play, Intel Play logo, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel Xeon, Intel XScale, IPLink, Itanium, LANDesk, LanRover, MCS, MMX, MMX logo, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, RemoteExpress, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside., The Journey Inside, TokenExpress, Trillium, VoiceBrick, Vtune, and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.

Datasheet

Contents

Contents

About This Document 9

Intel 80960Hx Processor 9 The Processor Family Key 80960Hx Features Execution Architecture Pipelined, Burst Bus On-Chip Caches and Data Priority Interrupt Guarded Memory Unit Dual Programmable Timers Processor Self Test Instruction Set Summary

Package Information

Pin Descriptions 80960Hx Mechanical
80960Hx PGA 80960Hx PQ4 Pinout Package Thermal Specifications Heat Sink PowerQuad4 Plastic Package Stepping Register Information Sources for Accessories

Electrical Specifications

Absolute Maximum Ratings Operating Conditions Recommended Connections VCC5 Pin Requirements VDIFF VCCPLL Pin Requirements DC Specifications AC

AC Test Conditions AC Timing Waveforms

Bus Waveforms
80960Hx Boundary Scan Chain Boundary Scan Description Language Example

Figures
1 80960Hx Block Diagram 9 2 80960Hx 168-Pin PGA from Top Pins Facing Down 3 80960Hx 168-Pin PGA from Bottom Pins Facing Up 4 80960Hx 208-Pin PQ4 5 Measuring 80960Hx PGA Case Temperature 6 80960Hx Device Identification

Datasheet

Contents
7 VCC5 Current-Limiting Resistor 38 8 AC Test 45 9 CLKIN 46 10 Output Delay Waveform 46 11 Output Delay Waveform 46 12 Output Float Waveform 47 13 Input Setup and Hold Waveform 47 14 NMI, XINT7:0 Input Setup and Hold 47 15 Hold Acknowledge Timings 48 16 Bus Backoff BOFF Timings 48 17 TCK Waveform 49 18 Input Setup and Hold Waveforms for TBSIS1 and 49 19 Output Delay and Output Float for TBSOV1 and TBSOF1 50 20 Output Delay and Output Float Waveform for TBSOV2 and TBSOF2 50 21 Input Setup and Hold Waveform for TBSIS2 and TBSIH2 50 22 Rise and Fall Time Derating at 85 °C and Minimum 51 23 ICC Active Power Supply vs. 51 24 ICC Active Thermal vs. 52 25 Output Delay or Hold vs. Load Capacitance 52 26 Output Delay vs. Temperature 53 27 Output Hold Times vs. Temperature 53 28 Output Delay vs. VCC 53 29 Cold Reset Waveform 54 30 Warm Reset Waveform 55 31 Entering ONCE 56 32 Non-Burst, Non-Pipelined Requests without Wait States 57 33 Non-Burst, Non-Pipelined Read Request with Wait States 58 34 Non-Burst, Non-Pipelined Write Request with Wait States 59 35 Burst, Non-Pipelined Read Request without Wait States, 32-Bit Bus 60 36 Burst, Non-Pipelined Read Request with Wait States, 32-Bit Bus 61 37 Burst, Non-Pipelined Write Request without Wait States, 32-Bit Bus 62 38 Burst, Non-Pipelined Write Request with Wait States, 32-Bit Bus 63 39 Burst, Non-Pipelined Read Request with Wait States, 16-Bit Bus 64 40 Burst, Non-Pipelined Read Request with Wait States, 8-Bit Bus 65 41 Non-Burst, Pipelined Read Request without Wait States, 32-Bit Bus 66 42 Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus 67 43 Burst, Pipelined Read Request without Wait States, 32-Bit Bus 68 44 Burst, Pipelined Read Request with Wait States, 32-Bit Bus 69 45 Burst, Pipelined Read Request with Wait States, 8-Bit Bus 70 46 Burst, Pipelined Read Request with Wait States, 16-Bit Bus 71 47 Using External 72 48 Terminating a Burst with BTERM 73 49 BREQ and BSTALL Operation 74 50 BOFF Functional Timing. BOFF occurs during a burst or non-burst data cycle. 75 51 HOLD Functional Timing 76 52 LOCK Delays HOLDA 77 53 FAIL Functional 77 54 A Summary of Aligned and Unaligned Transfers for 32-Bit 78 55 A Summary of Aligned and Unaligned Transfers for 32-Bit Regions Continued 79 56 A Summary of Aligned and Unaligned Transfers for 16-Bit 80

Datasheet

Contents
57 A Summary of Aligned and Unaligned Transfers for 8-Bit 58 Idle Bus Operation 59 Bus States

Tables
1 80960Hx Product Description 9 2 Fail Codes For BIST bit 7 = 1 3 Remaining Fail Codes bit 7 = 0 4 80960Hx Instruction Set 5 80960HA/HD/HT Package Types and 6 Pin Description Nomenclature 7 80960Hx Processor Family Pin 8 80960Hx 168-Pin PGA Name 9 80960Hx 168-Pin PGA Number Order 10 80960Hx PQ4 Name 11 80960Hx PQ4 Number Order 13 80960Hx 168-Pin PGA Package Thermal Characteristics 12 Maximum TA at Various Airflows in °C PGA Package Only 15 80960Hx 208-Pin PQ4 Package Thermal 14 Maximum TA at Various Airflows in °C PQ4 Package 17 80960Hx Device ID Model Types 18 Device ID Version Numbers for Different 16 Fields of 80960Hx Device ID 19 Absolute Maximum Ratings 20 Operating Conditions 21 VDIFF Specification for Dual Power Supply Requirements V, 5 V 22 80960Hx DC Characteristics 23 80960Hx AC 25 80960Hx Boundary Scan Test Signal Timings 24 AC Characteristics 26 80960Hx Boundary Scan Chain

Datasheet

Contents

History

August 2004

To address the fact that many of the package prefix variables have
changed, all package prefix variables in this document are now indicated
with an "x".

Formatted the datasheet in a new template.

In “32-Bit Parallel Architecture” on page 1:
• Removed operating frequency of 16/32 bus/core from 80960HD.
• Removed operating frequency of 20/60 bus/core from 80960HT.

In Table 5 “80960HA/HD/HT Package Types and Speeds” on page 14:

September 2002
• Removed core speed of 32 MHz and bus speed of 16 MHz, and order number A80960HD32-S-L2GG from the 168L PGA package, 80960HD device.
In Table 11 “80960Hx PQ4 Number Order” on page 29:
In Section “Absolute Maximum Ratings” on page 37:
• Added section.

In Table 22 “80960Hx DC Characteristics” on page 40:
• Added footnote 1 to ILO notes column for TDO pin.
• Added footnote 10 to CIN, COUT and CI/O pin.

Datasheet

Contents

July 1998 continued

History
007 continued

In Table 23 “80960Hx AC Characteristics” on page 42
• Added overbars where required.
• Modified TDVNH to list separate specifications for V and 5 V.
• Modified TOV2, TOH2 and TTVEL to reflect specific 80960HA, 80960HD and 80960HT values.

In Figure 23 “ICC Active Power Supply vs. Frequency” on page 51
• Changed ‘5’ to ‘0’ on the CLKIN Frequency axis.

In Figure 49 “BREQ and BSTALL Operation” on page 74
• Added figure and following text.

August 1997

Fixed several font and format issues.

Datasheet

Contents

This page intentionally left blank.

Datasheet
80960HA/HD/HT

About This Document

This document describes the parametric performance of Intel’s 80960Hx embedded superscalar microprocessors. Detailed descriptions for functional topics, other than parametric performance, are published in the Hx Microprocessor User’s Guide

In this document, ‘80960Hx’ and ‘i960 Hx processor’ refer to the products described in Table Throughout this document, information that is specific to each is clearly indicated.

Figure 80960Hx Block Diagram

JTAG Port Timers

Interrupt Programmable Port Interrupt Controller Multiply/Divide Unit

Execution Unit

Instruction Prefetch Queue Instruction Cache
16 Kbyte, Four-Way Set-Associative 128-Bit Cache Bus

Parallel Instruction Scheduler

Register-Side Memory-Side Machine Bus Machine Bus

Six-Port Register File 64-bit SRC1 Bus 32-bit Base Bus 64-bit SRC2 Bus 128-bit Load Bus 64-bit DST Bus 128-bit Store Bus

Guarded Memory Unit

Control

Memory Region Configuration

Bus Controller

Address

Bus Request Queues

Data

Data Cache 8 Kbyte, Four-Way Set-Associative

Data RAM - 2 Kbyte

Register Cache - 5 to 15 sets

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived A80960HT75SL2GP Datasheet file may be downloaded here without warranties.

Datasheet ID: A80960HT75SL2GP 638924