KU80960CA16

KU80960CA16 Datasheet

Part	Datasheet
KU80960CA16	KU80960CA16 (pdf)

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80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-bit Burst Bus with Pipelining s 32-bit Parallel Architecture Two Instructions/clock Execution Load/Store Architecture Sixteen 32-bit Global Registers Sixteen 32-bit Local Registers Manipulates 64-bit Fields 11 Addressing Modes Full Parallel Fault Model Supervisor Protection Model s Fast Procedure Call/Return Model Full Procedure Call in 4 Clocks s On-Chip Register Cache Caches Registers on Call/Ret Minimum of 6 Frames Provided Up to 15 Programmable Frames s On-Chip Instruction Cache 1 Kbyte Two-Way Set Associative 128-bit Path to Instruction Sequencer Cache-Lock Modes Cache-Off Mode s High Bandwidth On-Chip Data RAM 1 Kbyte On-Chip Data RAM Sustains 128 bits per Clock Access s Four On-Chip DMA Channels 59 Mbytes/s Fly-by Transfers 32 Mbytes/s Two-Cycle Transfers Data Chaining Data Packing/Unpacking Programmable Priority Method s 32-Bit Demultiplexed Burst Bus 128-bit Internal Data Paths to and from Registers Burst Bus for DRAM Interfacing Address Pipelining Option Fully Programmable Wait States Supports 8-, 16- or 32-bit Bus Widths Supports Unaligned Accesses Supervisor Protection Pin s Selectable Big or Little Endian Byte Ordering s High-Speed Interrupt Controller Up to 248 External Interrupts 32 Fully Programmable Priorities Multi-mode 8-bit Interrupt Port Four Internal DMA Interrupts Separate, Non-maskable Interrupt Pin Context Switch in 750 ns Typical Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel. INTEL CORPORATION, 1993 November 1993 Order Number 270727-006 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR CONTENTS PURPOSE 1 80960CA 1 The C-Series Core Pipelined, Burst Bus Flexible DMA Controller Priority Interrupt Controller Instruction Set Summary PACKAGE Introduction Pin Descriptions 4 80960CA Mechanical Data 11 CONTENTS LIST OF FIGURES Figure 1 80960CA Block Diagram 1 Figure 2 80960CA PGA from Top Pins Facing Down 13 Figure 3 80960CA PGA Pinout from Bottom Pins Facing Up 14 Figure 4 80960CA PQFP Pinout View from Top Side 17 Figure 5 Measuring 80960CA PGA and PQFP Case Temperature 18 Figure 6 Register g0 20 Figure 7 AC Test Load 29 Figure 8 Input and Output Clocks Waveform 29 Figure 9 CLKIN Waveform 29 Figure 10 Output Delay and Float Waveform 30 Figure 11 Input Setup and Hold Waveform 30 Figure 12 NMI, XINT7:0 Input Setup and Hold Waveform 31 Figure 13 Hold Acknowledge Timings 31 Figure 14 Bus Backoff BOFF Timings 32 Figure 15 Relative Timings Waveforms 33 Figure 16 Output Delay or Hold vs. Load Capacitance 33 Figure 17 Figure 18 Figure 19 Rise and Fall Time Derating at Highest Operating Temperature and Minimum VCC 34 ICC vs. Frequency and Temperature 34 Cold Reset Waveform 36 Figure 20 Warm Reset Waveform 37 Figure 21 Entering the ONCE State 38 Figure 22 Clock Synchronization in the 2-x Clock Mode 39 Figure 23 Clock Synchronization in the 1-x Clock Mode 39 Figure 24 Non-Burst, Non-Pipelined Requests Without Wait States 40 Figure 25 Non-Burst, Non-Pipelined Read Request With Wait States 41 Figure 26 Non-Burst, Non-Pipelined Write Request With Wait States 42 Figure 27 Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus 43 Figure 28 Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus 44 Figure 29 Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus 45

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80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR
• Two Instructions/Clock Sustained Execution
• Four 59 Mbytes/s DMA Channels with Data Chaining
• Demultiplexed 32-bit Burst Bus with Pipelining
s 32-bit Parallel Architecture Two Instructions/clock Execution Load/Store Architecture Sixteen 32-bit Global Registers Sixteen 32-bit Local Registers Manipulates 64-bit Fields 11 Addressing Modes Full Parallel Fault Model Supervisor Protection Model
s Fast Procedure Call/Return Model Full Procedure Call in 4 Clocks
s On-Chip Register Cache Caches Registers on Call/Ret Minimum of 6 Frames Provided Up to 15 Programmable Frames
s On-Chip Instruction Cache 1 Kbyte Two-Way Set Associative 128-bit Path to Instruction Sequencer Cache-Lock Modes Cache-Off Mode
s High Bandwidth On-Chip Data RAM 1 Kbyte On-Chip Data RAM Sustains 128 bits per Clock Access
s Four On-Chip DMA Channels 59 Mbytes/s Fly-by Transfers 32 Mbytes/s Two-Cycle Transfers Data Chaining Data Packing/Unpacking Programmable Priority Method
s 32-Bit Demultiplexed Burst Bus 128-bit Internal Data Paths to and from Registers Burst Bus for DRAM Interfacing Address Pipelining Option Fully Programmable Wait States Supports 8-, 16- or 32-bit Bus Widths Supports Unaligned Accesses Supervisor Protection Pin
s Selectable Big or Little Endian Byte Ordering
s High-Speed Interrupt Controller Up to 248 External Interrupts 32 Fully Programmable Priorities Multi-mode 8-bit Interrupt Port Four Internal DMA Interrupts Separate, Non-maskable Interrupt Pin Context Switch in 750 ns Typical

Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.

INTEL CORPORATION, 1993

November 1993

Order Number 270727-006
80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

CONTENTS

PURPOSE 1 80960CA 1

The C-Series Core Pipelined, Burst Bus Flexible DMA Controller Priority Interrupt Controller Instruction Set Summary PACKAGE Introduction Pin Descriptions 4 80960CA Mechanical Data 11

CONTENTS

LIST OF FIGURES

Figure 1 80960CA Block Diagram 1

Figure 2 80960CA PGA from Top Pins Facing Down 13

Figure 3 80960CA PGA Pinout from Bottom Pins Facing Up 14

Figure 4 80960CA PQFP Pinout View from Top Side 17

Figure 5 Measuring 80960CA PGA and PQFP Case Temperature 18

Figure 6 Register g0 20

Figure 7 AC Test Load 29

Figure 8 Input and Output Clocks Waveform 29

Figure 9 CLKIN Waveform 29

Figure 10 Output Delay and Float Waveform 30

Figure 11 Input Setup and Hold Waveform 30

Figure 12 NMI, XINT7:0 Input Setup and Hold Waveform 31

Figure 13 Hold Acknowledge Timings 31

Figure 14 Bus Backoff BOFF Timings 32

Figure 15 Relative Timings Waveforms 33

Figure 16 Output Delay or Hold vs. Load Capacitance 33

Figure 17 Figure 18 Figure 19

Rise and Fall Time Derating at Highest Operating Temperature and Minimum VCC 34 ICC vs. Frequency and Temperature 34 Cold Reset Waveform 36

Figure 20 Warm Reset Waveform 37

Figure 21 Entering the ONCE State 38

Figure 22 Clock Synchronization in the 2-x Clock Mode 39

Figure 23 Clock Synchronization in the 1-x Clock Mode 39

Figure 24 Non-Burst, Non-Pipelined Requests Without Wait States 40

Figure 25 Non-Burst, Non-Pipelined Read Request With Wait States 41

Figure 26 Non-Burst, Non-Pipelined Write Request With Wait States 42

Figure 27 Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus 43

Figure 28 Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus 44

Figure 29 Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus 45

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Datasheet ID: KU80960CA16 638923