IS66WVE4M16ALL-70BLI

IS66WVE4M16ALL-70BLI Datasheet

IS66WVE4M16ALL IS67WVE4M16ALL

Part	Datasheet
IS66WVE4M16ALL-70BLI	IS66WVE4M16ALL-70BLI (pdf)

Related Parts	Information
IS66WVE4M16EALL-70BLI	IS66WVE4M16EALL-70BLI
IS66WVE4M16ALL-7010BLI	IS66WVE4M16ALL-7010BLI
IS66WVE4M16ALL-7010BLI-TR	IS66WVE4M16ALL-7010BLI-TR
IS66WVE4M16ALL-70BLI-TR	IS66WVE4M16ALL-70BLI-TR
IS66WVE4M16EALL-70BLI-TR	IS66WVE4M16EALL-70BLI-TR

PDF Datasheet Preview
IS66WVE4M16ALL IS67WVE4M16ALL 1.8V Core Async/Page PSRAM Overview The IS66WVE4M16ALL is an integrated memory device containing 64Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 4M words by 16 bits. The device includes several power saving modes Partial Array Refresh mode where data is retained in a portion of the array and Deep Power Down mode. Both these modes reduce standby current drain. The die has separate power rails, VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core. Asynchronous and page mode interface Dual voltage rails for optional performance  VDD 1.8V, VDDQ 1.8V Page mode read access  Interpage Read access 70ns  Intrapage Read access 20ns Low Power Consumption  Asynchronous Operation < 30 mA  Intrapage Read < 18mA  Standby < 180 uA max.  Deep power-down DPD < 3uA Typ Low Power Feature  Temperature Controlled Refresh  Partial Array Refresh  Deep power-down DPD mode Operating temperature Range Industrial and Automotive, A1 -40°C~85°C Package 48-ball TFBGA, 48-pin TSOP-I Notes The 48-pin TSOP-I package option is not yet available. Please contact SRAM marketing at for additional information. Copyright 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a. the risk of injury or damage has been minimized; b. the user assume all such risks and c. potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances IS66WVE4M16ALL IS67WVE4M16ALL PSRAM products are high-speed, CMOS pseudo-static random access memory developed for low-power, portable applications. The 64Mb DRAM core device is organized as 4 Meg x 16 bits. These devices include the industry-standard, asynchronous memory interface found on other low-power SRAM or pseudo-SRAM PSRAM offerings. For seamless operation on an asynchronous memory bus, PSRAM products incorporated a transparent self-refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. A user-accessible configuration registers CR defines how the PSRAM device performs onchip refresh and whether page mode read accesses are permitted. This register is automatically loaded with a default setting during power-up and can be updated at any time during normal operation. Special attention has been focused on current consumption during self-refresh. This product includes two system-accessible mechanisms to minimize refresh current. Setting sleep enable ZZ# to LOW enables one of two low-power modes partial-array refresh PAR or deep power-down DPD . PAR limits refresh to only that part of the DRAM array that contains essential data. DPD halts refresh operation altogether and is used when no vital information is stored in the device. The system-configurable refresh mechanisms are accessed through the CR. A0~A21 Address Decode Logic Configuration Register CR 4096K X 16 DRAM Memory Array Input /Output Mux And Buffers CE# WE# OE# LB# UB# ZZ# Control Logic [ Functional Block Diagram] - DQ0~DQ15 2 IS66WVE4M16ALL IS67WVE4M16ALL 48Ball TFBGA Ball Assignment LB# OE# DQ8 UB# CE# DQ0 DQ9 DQ10 DQ1 DQ2 VSSQ DQ11 A17 DQ3 VDD VDDQ DQ12 A21 DQ14 DQ13 A14 DQ15 A19 Ordering Information VDD = 1.8V Industrial Temperature Range -40oC to +85oC Config. 4Mx16 Speed ns Order Part No. IS66WVE4M16ALL-70BLI Package 48-ball TFBGA, Lead-free Automotive, A1 Temperature Range -40oC to +85oC Config. 4Mx16 Speed ns Order Part No. IS67WVE4M16ALL-70BLA1 Package 48-ball TFBGA, Lead-free Notes The 48-pin TSOP-I package option is not yet available. Please contact SRAM marketing at for additional information. 48-pin TSOP-I package configuration IS66WVE4M16ALL IS67WVE4M16ALL IS66WVE4M16ALL IS67WVE4M16ALL

PDF Datasheet Preview

IS66WVE4M16ALL IS67WVE4M16ALL
1.8V Core Async/Page PSRAM

Overview The IS66WVE4M16ALL is an integrated memory device containing 64Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 4M words by 16 bits. The device includes several power saving modes Partial Array Refresh mode where data is retained in a portion of the array and Deep Power Down mode. Both these modes reduce standby current drain. The die has separate power rails, VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core.

Asynchronous and page mode interface Dual voltage rails for optional performance
 VDD 1.8V, VDDQ 1.8V Page mode read access
 Interpage Read access 70ns  Intrapage Read access 20ns Low Power Consumption  Asynchronous Operation < 30 mA  Intrapage Read < 18mA  Standby < 180 uA max.  Deep power-down DPD < 3uA Typ

Low Power Feature  Temperature Controlled Refresh  Partial Array Refresh  Deep power-down DPD mode

Operating temperature Range Industrial and Automotive, A1 -40°C~85°C

Package 48-ball TFBGA, 48-pin TSOP-I

Notes The 48-pin TSOP-I package option is not yet available. Please contact SRAM marketing at for
additional information.

Copyright 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a. the risk of injury or damage has been minimized;
b. the user assume all such risks and
c. potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

IS66WVE4M16ALL IS67WVE4M16ALL

PSRAM products are high-speed, CMOS pseudo-static random access memory developed for low-power, portable applications. The 64Mb DRAM core device is organized as 4 Meg x 16 bits. These devices include the industry-standard, asynchronous memory interface found on other low-power SRAM or pseudo-SRAM PSRAM offerings. For seamless operation on an asynchronous memory bus, PSRAM products incorporated a transparent self-refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. A user-accessible configuration registers CR defines how the PSRAM device performs onchip refresh and whether page mode read accesses are permitted. This register is automatically loaded with a default setting during power-up and can be updated at any time during normal operation. Special attention has been focused on current consumption during self-refresh. This product includes two system-accessible mechanisms to minimize refresh current. Setting sleep enable ZZ# to LOW enables one of two low-power modes partial-array refresh PAR or deep power-down DPD . PAR limits refresh to only that part of the DRAM array that contains essential data. DPD halts refresh operation altogether and is used when no vital information is stored in the device. The system-configurable refresh mechanisms are accessed through the CR.

A0~A21

Address Decode Logic

Configuration Register CR
4096K X 16 DRAM

Memory Array

Input /Output

Mux And Buffers

CE# WE# OE# LB# UB# ZZ#

Control Logic
[ Functional Block Diagram] -

DQ0~DQ15 2

IS66WVE4M16ALL IS67WVE4M16ALL
48Ball TFBGA Ball Assignment

LB# OE#

DQ8 UB#

CE# DQ0

DQ9 DQ10

DQ1 DQ2

VSSQ DQ11 A17

DQ3 VDD

VDDQ DQ12 A21

DQ14 DQ13 A14

DQ15 A19
Ordering Information VDD = 1.8V

Industrial Temperature Range -40oC to +85oC

Config. 4Mx16

Speed ns

Order Part No. IS66WVE4M16ALL-70BLI

Package 48-ball TFBGA, Lead-free

Automotive, A1 Temperature Range -40oC to +85oC

Config. 4Mx16

Speed ns

Order Part No. IS67WVE4M16ALL-70BLA1

Package 48-ball TFBGA, Lead-free

Notes The 48-pin TSOP-I package option is not yet available. Please contact SRAM marketing at
for additional information.
48-pin TSOP-I package configuration

IS66WVE4M16ALL IS67WVE4M16ALL

IS66WVE4M16ALL IS67WVE4M16ALL

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IS66WVE4M16ALL-70BLI Datasheet file may be downloaded here without warranties.

Datasheet ID: IS66WVE4M16ALL-70BLI 639328