IS67WVC4M16ALL-7010BLA1

IS67WVC4M16ALL-7010BLA1 Datasheet

IS66WVC4M16ALL IS67WVC4M16ALL

Part	Datasheet
IS67WVC4M16ALL-7010BLA1	IS67WVC4M16ALL-7010BLA1 (pdf)

Related Parts	Information
IS66WVC4M16ALL-7010BLI	IS66WVC4M16ALL-7010BLI
IS66WVC4M16ALL-7010BLI-TR	IS66WVC4M16ALL-7010BLI-TR
IS67WVC4M16ALL-7010BLA-TR	IS67WVC4M16ALL-7010BLA-TR

PDF Datasheet Preview
IS66WVC4M16ALL IS67WVC4M16ALL 64Mb Async/Page/Burst CellularRAM Overview The IS66WVC4M16ALL is an integrated memory device containing 64Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 4M words by 16 bits. The device includes several power saving modes Reduced Array Refresh mode where data is retained in a portion of the array and Temperature Controlled Refresh. Both these modes reduce standby current drain. The device can be operated in a standard asynchronous mode and high performance burst mode. The die has separate power rails, VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core. Single device supports asynchronous , page, and burst operation Mixed Mode supports asynchronous write and synchronous read operation Dual voltage rails for optional performance  VDD 1.7V~1.95V, VDDQ 1.7V~1.95V Asynchronous mode read access 70ns Interpage Read access 70ns Intrapage Read access 20ns Burst mode for Read and Write operation  4, 8, 16,32 or Continuous Low Power Consumption  Asynchronous Operation < 25 mA  Intrapage Read < 18mA  Burst operation < 35 mA  Standby < 180 uA max.  Deep power-down DPD < 3uA Typ Low Power Feature  Reduced Array Refresh  Temperature Controlled Refresh  Deep power-down DPD mode Operation Frequency up to 104Mhz Operating temperature Range Industrial -40°C~85°C Automotive A1 -40°C~85°C Package 54-ball VFBGA Copyright 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a. the risk of injury or damage has been minimized; b. the user assume all such risks and c. potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances IS66WVC4M16ALL IS67WVC4M16ALL CellularRAM Trademark of MicronTechnology Inc. products are high-speed, CMOS pseudo-static random access memory developed for low-power, portable applications. The 64Mb DRAM core device is organized as 4 Meg x 16 bits. This device is a variation of the industry-standard Flash control interface that dramatically increase READ/WRITE bandwidth compared with other low-power SRAM or Pseudo SRAM offerings. To operate seamlessly on a burst Flash bus, CellularRAM products have incorporated a transparent self-refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. Two user-accessible control registers define device operation. The bus configuration register BCR defines how the CellularRAM device interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register RCR is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up and can be updated anytime during normal operation. Special attention has been focused on standby current consumption during self refresh. CellularRAM products include three mechanisms to minimize standby current. Partial array refresh PAR enables the system to limit refresh to only that part of the DRAM array that contains essential data. Temperature-compensated refresh TCR uses an on-chip sensor to adjust the refresh rate to match the device temperature the refresh rate decreases at lower temperatures to minimize current consumption during standby. Deep power-down DPD enables the system to halt the refresh operation altogether when no vital information is stored in the device. The system-configurable refresh mechanisms are adjusted through the RCR. This CellularRAM device is compliant with the industry-standard CellularRAM feature set established by the CellularRAM Workgroup. It includes support for both variable and fixed latency, with three drive strengths, a variety of wrap options, and a device ID register DIDR . A0~A21 CE# WE# OE# CLK ADV# CRE LB# UB# WAIT Control Logic Address Decode Logic Refresh Configuration Register Device ID Register DIDR Bus Configuration Register 4096K X 16 DRAM Memory Array [ Functional Block Diagram] Input /Output Mux And Buffers DQ0~DQ15 2 54Ball VFBGA Ball Assignment IS66WVC4M16ALL IS67WVC4M16ALL [Top View] Ball Down IS66WVC4M16ALL IS67WVC4M16ALL Signal Descriptions All signals for the device are listed below in Table Table Signal Descriptions Ordering Information VDD = 1.8V Industrial Temperature Range -40oC to +85oC Config. 4Mx16 Speed ns Frequency MHz 104 Order Part No. IS66WVC4M16ALL-7010BLI IS66WVC4M16ALL-7008BLI Package 54-ball VFBGA 54-ball VFBGA Automotive A1 Temperature Range -40oC to +85oC Config. 4Mx16 Speed ns Frequency MHz Order Part No. IS67WVC4M16ALL-7010BLA1 Package 54-ball VFBGA IS66WVC4M16ALL IS67WVC4M16ALL

PDF Datasheet Preview

IS66WVC4M16ALL IS67WVC4M16ALL
64Mb Async/Page/Burst CellularRAM

Overview The IS66WVC4M16ALL is an integrated memory device containing 64Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 4M words by 16 bits. The device includes several power saving modes Reduced Array Refresh mode where data is retained in a portion of the array and Temperature Controlled Refresh. Both these modes reduce standby current drain. The device can be operated in a standard asynchronous mode and high performance burst mode. The die has separate power rails, VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core.

Single device supports asynchronous , page, and burst operation

Mixed Mode supports asynchronous write and synchronous read operation

Dual voltage rails for optional performance  VDD 1.7V~1.95V, VDDQ 1.7V~1.95V

Asynchronous mode read access 70ns Interpage Read access 70ns Intrapage Read access 20ns

Burst mode for Read and Write operation  4, 8, 16,32 or Continuous

Low Power Consumption  Asynchronous Operation < 25 mA  Intrapage Read < 18mA  Burst operation < 35 mA  Standby < 180 uA max.  Deep power-down DPD < 3uA Typ

Low Power Feature  Reduced Array Refresh  Temperature Controlled Refresh  Deep power-down DPD mode

Operation Frequency up to 104Mhz Operating temperature Range

Industrial -40°C~85°C Automotive A1 -40°C~85°C Package 54-ball VFBGA

Copyright 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a. the risk of injury or damage has been minimized;
b. the user assume all such risks and
c. potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

IS66WVC4M16ALL IS67WVC4M16ALL

CellularRAM Trademark of MicronTechnology Inc. products are high-speed, CMOS pseudo-static random access memory developed for low-power, portable applications. The 64Mb DRAM core device is organized as 4 Meg x 16 bits. This device is a variation of the industry-standard Flash control interface that dramatically increase READ/WRITE bandwidth compared with other low-power SRAM or Pseudo SRAM offerings. To operate seamlessly on a burst Flash bus, CellularRAM products have incorporated a transparent self-refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. Two user-accessible control registers define device operation. The bus configuration register BCR defines how the CellularRAM device interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register RCR is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up and can be updated anytime during normal operation. Special attention has been focused on standby current consumption during self refresh. CellularRAM products include three mechanisms to minimize standby current. Partial array refresh PAR enables the system to limit refresh to only that part of the DRAM array that contains essential data. Temperature-compensated refresh TCR uses an on-chip sensor to adjust the refresh rate to match the device temperature the refresh rate decreases at lower temperatures to minimize current consumption during standby. Deep power-down DPD enables the system to halt the refresh operation altogether when no vital information is stored in the device. The system-configurable refresh mechanisms are adjusted through the RCR. This CellularRAM device is compliant with the industry-standard CellularRAM feature set established by the CellularRAM Workgroup. It includes support for both variable and fixed latency, with three drive strengths, a variety of wrap options, and a device ID register DIDR .

A0~A21

CE# WE# OE#

CLK ADV#

CRE LB# UB# WAIT

Control Logic

Address Decode Logic

Refresh Configuration Register

Device ID Register DIDR

Bus Configuration Register
4096K X 16 DRAM

Memory Array
[ Functional Block Diagram]

Input /Output

Mux And Buffers

DQ0~DQ15 2
54Ball VFBGA Ball Assignment

IS66WVC4M16ALL IS67WVC4M16ALL
[Top View] Ball Down

IS66WVC4M16ALL IS67WVC4M16ALL

Signal Descriptions

All signals for the device are listed below in Table

Table Signal Descriptions
Ordering Information VDD = 1.8V Industrial Temperature Range -40oC to +85oC

Config. 4Mx16

Speed ns

Frequency MHz 104

Order Part No. IS66WVC4M16ALL-7010BLI IS66WVC4M16ALL-7008BLI

Package 54-ball VFBGA 54-ball VFBGA

Automotive A1 Temperature Range -40oC to +85oC

Config. 4Mx16

Speed ns

Frequency MHz

Order Part No. IS67WVC4M16ALL-7010BLA1

Package 54-ball VFBGA

IS66WVC4M16ALL IS67WVC4M16ALL

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IS67WVC4M16ALL-7010BLA1 Datasheet file may be downloaded here without warranties.

Datasheet ID: IS67WVC4M16ALL-7010BLA1 639326