IS61NLP12832A-200TQLI

IS61NLP12832A-200TQLI Datasheet

IS61NLP12832A IS61NLP12836A/IS61NVP12836A IS61NLP25618A/IS61NVP25618A

Part	Datasheet
IS61NLP12832A-200TQLI	IS61NLP12832A-200TQLI (pdf)

Related Parts	Information
IS61NLP12832A-200TQLI-TR	IS61NLP12832A-200TQLI-TR

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IS61NLP12832A IS61NLP12836A/IS61NVP12836A IS61NLP25618A/IS61NVP25618A 128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE 'NO WAIT' STATE BUS SRAM OCTOBER 2006 • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W Read/Write control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP, 165-ball PBGA and 119- ball PBGA packages • Power supply: NVP VDD 2.5V ± 5% , VDDQ 2.5V ± 5% NLP VDD 3.3V ± 5% , VDDQ 3.3V/2.5V ± 5% • Industrial temperature available • Lead-free available The 4 Meg 'NLP/NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 128K words by 32 bits, 128K words by 36 bits, and 256K words by 18 bits, fabricated with ISSI's advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin MODE defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected. FAST ACCESS TIME Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency -250 -200 Units Copyright 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. 1-800-379-4774 10/03/06 IS61NLP12832A IS61NLP12836A/IS61NVP12836A IS61NLP25618A/IS61NVP25618A BLOCK DIAGRAM ISSI x 32/x 36 A [0:16] or ADDRESS x 18 A [0:17] REGISTER A2-A16 or A2-A17 MODE A0-A1 BURST ADDRESS COUNTER A'0-A'1 128Kx32 128Kx36 256Kx18 MEMORY ARRAY K DATA-IN REGISTER CONTROL LOGIC K CE CE2 ORDERING INFORMATION VDD = 3.3V/VDDQ = 2.5V/3.3V Commercial Range 0°C to +70°C Access Time 250 200 250 200 250 200 Order Part Number 128Kx32 IS61NLP12832A-250TQ IS61NLP12832A-250B3 IS61NLP12832A-250B2 IS61NLP12832A-200TQ IS61NLP12832A-200B3 IS61NLP12832A-200B2 128Kx36 IS61NLP12836A-250TQ IS61NLP12836A-250B3 IS61NLP12836A-250B2 IS61NLP12836A-200TQ IS61NLP12836A-200B3 IS61NLP12836A-200B2 256Kx18 IS61NLP25618A-250TQ IS61NLP25618A-250B3 IS61NLP25618A-250B2 IS61NLP25618A-200TQ IS61NLP25618A-200B3 IS61NLP25618A-200B2 ISSI Package 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA Integrated Silicon Solution, Inc. 1-800-379-4774 10/03/06 IS61NLP12832A IS61NLP12836A/IS61NVP12836A IS61NLP25618A/IS61NVP25618A ORDERING INFORMATION VDD = 3.3V/VDDQ = 2.5V/3.3V Industrial Range -40°C to +85°C Access Time 250 200 250 200 250 200 Order Part Number 128Kx32 IS61NLP12832A-250TQI IS61NLP12832A-250B3I IS61NLP12832A-250B2I IS61NLP12832A-200TQI IS61NLP12832A-200TQLI IS61NLP12832A-200B3I IS61NLP12832A-200B2I 128Kx36 IS61NLP12836A-250TQI IS61NLP12836A-250B3I IS61NLP12836A-250B2I IS61NLP12836A-200TQI IS61NLP12836A-200TQLI IS61NLP12836A-200B3I IS61NLP12836A-200B2I 256Kx18 IS61NLP25618A-250TQI IS61NLP25618A-250B3I IS61NLP25618A-250B2I IS61NLP25618A-200TQI IS61NLP25618A-200TQLI IS61NLP25618A-200B3I IS61NLP25618A-200B2I ISSI Package 100 TQFP 165 PBGA 119 PBGA 100 TQFP 100 TQFP, Lead-free 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 100 TQFP 100 TQFP, Lead-free 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 100 TQFP 100 TQFP, Lead-free 165 PBGA 119 PBGA Integrated Silicon Solution, Inc. 1-800-379-4774 10/03/06 IS61NLP12832A IS61NLP12836A/IS61NVP12836A IS61NLP25618A/IS61NVP25618A ORDERING INFORMATION VDD = 2.5V/VDDQ = 2.5V Commercial Range 0°C to +70°C Access Time 250 200 250 200 Order Part Number 128Kx36 IS61NVP12836A-250TQ IS61NVP12836A-250B3 IS61NVP12836A-250B2 IS61NVP12836A-200TQ IS61NVP12836A-200B3 IS61NVP12836A-200B2 256Kx18 IS61NVP25618A-250TQ IS61NVP25618A-250B3 IS61NVP25618A-250B2 IS61NVP25618A-200TQ IS61NVP25618A-200B3 IS61NVP25618A-200B2 Industrial Range -40°C to +85°C Access Time 250 200 250 200 Order Part Number 128Kx36 IS61NVP12836A-250TQI IS61NVP12836A-250B3I IS61NVP12836A-250B2I IS61NVP12836A-200TQI IS61NVP12836A-200B3I IS61NVP12836A-200B2I 256Kx18 IS61NVP25618A-250TQI IS61NVP25618A-250B3I IS61NVP25618A-250B2I IS61NVP25618A-200TQI IS61NVP25618A-200B3I IS61NVP25618A-200B2I ISSI Package 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA Package 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA Integrated Silicon Solution, Inc. 1-800-379-4774 10/03/06 PACKAGING INFORMATION Plastic Ball Grid Array Package Code B 119-pin b 119X 7 6 5 4 32 1 SEATING PLANE MILLIMETERS INCHES Sym. Min. Max. Leads Min. Max.

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IS61NLP12832A IS61NLP12836A/IS61NVP12836A IS61NLP25618A/IS61NVP25618A
128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE 'NO WAIT' STATE BUS SRAM

OCTOBER 2006
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single R/W Read/Write control pin
• Clock controlled, registered address,
data and control
• Interleaved or linear burst sequence control using

MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Power Down mode
• Common data inputs and data outputs
• CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP, 165-ball PBGA and 119-
ball PBGA packages
• Power supply:

NVP VDD 2.5V ± 5% , VDDQ 2.5V ± 5% NLP VDD 3.3V ± 5% , VDDQ 3.3V/2.5V ± 5%
• Industrial temperature available
• Lead-free available

The 4 Meg 'NLP/NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 128K words by 32 bits, 128K words by 36 bits,
and 256K words by 18 bits, fabricated with ISSI's advanced

CMOS technology.

Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit.

All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values.

All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW.

Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written.

A burst mode pin MODE defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected.

FAST ACCESS TIME

Symbol tKQ tKC

Parameter Clock Access Time Cycle Time Frequency
-250
-200

Units

Copyright 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. 1-800-379-4774
10/03/06

IS61NLP12832A IS61NLP12836A/IS61NVP12836A IS61NLP25618A/IS61NVP25618A

BLOCK DIAGRAM

ISSI
x 32/x 36 A [0:16] or ADDRESS
x 18 A [0:17]

REGISTER

A2-A16 or A2-A17

MODE A0-A1

BURST ADDRESS COUNTER

A'0-A'1
128Kx32 128Kx36 256Kx18 MEMORY ARRAY

K DATA-IN REGISTER

CONTROL

LOGIC K

CE CE2
ORDERING INFORMATION VDD = 3.3V/VDDQ = 2.5V/3.3V Commercial Range 0°C to +70°C

Access Time 250 200
250 200
250 200

Order Part Number
128Kx32

IS61NLP12832A-250TQ IS61NLP12832A-250B3 IS61NLP12832A-250B2

IS61NLP12832A-200TQ IS61NLP12832A-200B3 IS61NLP12832A-200B2
128Kx36

IS61NLP12836A-250TQ IS61NLP12836A-250B3 IS61NLP12836A-250B2

IS61NLP12836A-200TQ IS61NLP12836A-200B3 IS61NLP12836A-200B2
256Kx18

IS61NLP25618A-250TQ IS61NLP25618A-250B3 IS61NLP25618A-250B2

IS61NLP25618A-200TQ IS61NLP25618A-200B3 IS61NLP25618A-200B2

ISSI

Package
100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA
100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA
100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA

Integrated Silicon Solution, Inc. 1-800-379-4774
10/03/06

IS61NLP12832A IS61NLP12836A/IS61NVP12836A IS61NLP25618A/IS61NVP25618A
ORDERING INFORMATION VDD = 3.3V/VDDQ = 2.5V/3.3V Industrial Range -40°C to +85°C

Access Time 250 200
250 200
250 200

Order Part Number
128Kx32

IS61NLP12832A-250TQI IS61NLP12832A-250B3I IS61NLP12832A-250B2I

IS61NLP12832A-200TQI IS61NLP12832A-200TQLI IS61NLP12832A-200B3I IS61NLP12832A-200B2I
128Kx36

IS61NLP12836A-250TQI IS61NLP12836A-250B3I IS61NLP12836A-250B2I

IS61NLP12836A-200TQI IS61NLP12836A-200TQLI IS61NLP12836A-200B3I IS61NLP12836A-200B2I
256Kx18

IS61NLP25618A-250TQI IS61NLP25618A-250B3I IS61NLP25618A-250B2I

IS61NLP25618A-200TQI IS61NLP25618A-200TQLI IS61NLP25618A-200B3I IS61NLP25618A-200B2I

ISSI

Package
100 TQFP 165 PBGA 119 PBGA 100 TQFP 100 TQFP, Lead-free 165 PBGA 119 PBGA
100 TQFP 165 PBGA 119 PBGA 100 TQFP 100 TQFP, Lead-free 165 PBGA 119 PBGA
100 TQFP 165 PBGA 119 PBGA 100 TQFP 100 TQFP, Lead-free 165 PBGA 119 PBGA

Integrated Silicon Solution, Inc. 1-800-379-4774
10/03/06

IS61NLP12832A IS61NLP12836A/IS61NVP12836A IS61NLP25618A/IS61NVP25618A
ORDERING INFORMATION VDD = 2.5V/VDDQ = 2.5V Commercial Range 0°C to +70°C

Access Time 250 200
250 200

Order Part Number
128Kx36

IS61NVP12836A-250TQ IS61NVP12836A-250B3 IS61NVP12836A-250B2

IS61NVP12836A-200TQ IS61NVP12836A-200B3 IS61NVP12836A-200B2
256Kx18

IS61NVP25618A-250TQ IS61NVP25618A-250B3 IS61NVP25618A-250B2

IS61NVP25618A-200TQ IS61NVP25618A-200B3 IS61NVP25618A-200B2

Industrial Range -40°C to +85°C

Access Time 250 200
250 200

Order Part Number
128Kx36

IS61NVP12836A-250TQI IS61NVP12836A-250B3I IS61NVP12836A-250B2I

IS61NVP12836A-200TQI IS61NVP12836A-200B3I IS61NVP12836A-200B2I
256Kx18

IS61NVP25618A-250TQI IS61NVP25618A-250B3I IS61NVP25618A-250B2I

IS61NVP25618A-200TQI IS61NVP25618A-200B3I IS61NVP25618A-200B2I

ISSI

Package
100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA
100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA

Package
100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA
100 TQFP 165 PBGA 119 PBGA 100 TQFP 165 PBGA 119 PBGA

Integrated Silicon Solution, Inc. 1-800-379-4774
10/03/06

PACKAGING INFORMATION

Plastic Ball Grid Array Package Code B 119-pin
b 119X
7 6 5 4 32 1

SEATING PLANE

MILLIMETERS

INCHES

Sym. Min.

Max.

Leads

Min.

Max.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IS61NLP12832A-200TQLI Datasheet file may be downloaded here without warranties.

Datasheet ID: IS61NLP12832A-200TQLI 639309