IS43R16800A-5TL-TR

IS43R16800A-5TL-TR Datasheet

IS43R16800A

Part	Datasheet
IS43R16800A-5TL-TR	IS43R16800A-5TL-TR (pdf)

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IS43R16800A 8Meg x 16 128-MBIT DDR SDRAM • Clock Frequency 200, 125 MHz • Power supply VDD and VDDQ 2.6V • SSTL 2 interface • Four internal banks to hide row Pre-charge and Active operations • Commands and addresses register on positive clock edges CLK • Bi-directional Data Strobe signal for data cap- ture • Differential clock inputs CLK and CLK for two data accesses per clock cycle • Data Mask feature for Writes supported • DLL aligns data I/O and Data Strobe transitions with clock inputs • Half-strength and Matched drive strength options • Programmable burst length for Read and Write operations • Programmable CAS Latency 3 clocks • Programmable burst sequence sequential or interleaved • Burst concatenation and truncation supported for maximum data throughput • Auto Pre-charge option for each Read or Write burst • 4096 refresh cycles every 64ms • Auto Refresh and Self Refresh Modes • Pre-charge Power Down and Active Power Down Modes • Industrial Temperature Availability • Lead-free Availability PRELIMINARY INFORMATION JULY 2005 DEVICE OVERVIEW ISSI’s 128-Mbit DDR SDRAM achieves high-speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 134,217,728-bit memory array is internally organized as four banks of 32M-bit to allow concurrent operations. The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. The programmable features of burst length, burst sequence and CAS latency enable further advantages. The device is available in 16-bit data word size. Input data is registered on the I/O pins on both edges of Data Strobe signal s , while output data is referenced to both edges of Data Strobe and both edges of CLK. Commands are registered on the positive edges of CLK. Auto Refresh, Active Power Down, and Pre-charge Power Down modes are enabled by using clock enable CKE and other inputs in an industry-standard sequence. All input and output voltage levels are compatible with SSTL IS43R16800A 1M x16x8 Banks VDD 2.6V VDDQ 2.6V 66-pin TSOP-II Copyright 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. 1-800-379-4774 07/11/05 IS43R16800A ISSI FUNCTIONAL BLOCK DIAGRAM X16 CLK CKE CS RAS CAS WE COMMAND DECODER & CLOCK GENERATOR MODE REGISTER ADDRESS ORDERING INFORMATION Commercial Range 0°C to +70°C Frequency 400 MHz 400 MHz Speed ns 5 Order Part No. IS43R16800A-5T IS43R16800A-5TL Package 66-pin TSOP-II 66-pin TSOP-II, Lead-free Integrated Silicon Solution, Inc. 1-800-379-4774 07/11/05 PACKAGING INFORMATION Plastic TSOP 66-pin Package Code T Type II N/2+1 E1 E Notes Controlling dimension millimieters, unless otherwise specified. BSC = Basic lead spacing between centers. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. Formed leads shall be planar with respect to one another within inches at the seating plane. SEATING PLANE Plastic TSOP T - Type II Millimeters Inches Symbol Min Max Min Max Ref. Std. No. Leads N ZD REF 0° 8° 0° 8° Integrated Silicon Solution, Inc. 1-800-379-4774 08/09/05

PDF Datasheet Preview

IS43R16800A
8Meg x 16 128-MBIT DDR SDRAM
• Clock Frequency 200, 125 MHz
• Power supply VDD and VDDQ 2.6V
• SSTL 2 interface
• Four internal banks to hide row Pre-charge
and Active operations
• Commands and addresses register on positive
clock edges CLK
• Bi-directional Data Strobe signal for data cap-
ture
• Differential clock inputs CLK and CLK for
two data accesses per clock cycle
• Data Mask feature for Writes supported
• DLL aligns data I/O and Data Strobe transitions
with clock inputs
• Half-strength and Matched drive strength
options
• Programmable burst length for Read and Write
operations
• Programmable CAS Latency 3 clocks
• Programmable burst sequence sequential or
interleaved
• Burst concatenation and truncation supported
for maximum data throughput
• Auto Pre-charge option for each Read or Write
burst
• 4096 refresh cycles every 64ms
• Auto Refresh and Self Refresh Modes
• Pre-charge Power Down and Active Power

Down Modes
• Industrial Temperature Availability
• Lead-free Availability

PRELIMINARY INFORMATION JULY 2005

DEVICE OVERVIEW

ISSI’s 128-Mbit DDR SDRAM achieves high-speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 134,217,728-bit memory array is internally organized as four banks of 32M-bit to allow concurrent operations. The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. The programmable features of burst length, burst sequence and CAS latency enable further advantages. The device is available in 16-bit data word size. Input data is registered on the I/O pins on both edges of Data Strobe signal s , while output data is referenced to both edges of Data Strobe and both edges of CLK. Commands are registered on the positive edges of CLK. Auto Refresh, Active Power Down, and Pre-charge Power Down modes are enabled by using clock enable CKE and other inputs in an industry-standard sequence. All input and output voltage levels are compatible with SSTL

IS43R16800A 1M x16x8 Banks VDD 2.6V VDDQ 2.6V 66-pin TSOP-II

Copyright 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. 1-800-379-4774
07/11/05

IS43R16800A

ISSI

FUNCTIONAL BLOCK DIAGRAM X16

CLK CKE

CS RAS CAS WE

COMMAND DECODER
& CLOCK GENERATOR

MODE REGISTER

ADDRESS
ORDERING INFORMATION Commercial Range 0°C to +70°C

Frequency 400 MHz 400 MHz

Speed ns 5

Order Part No. IS43R16800A-5T IS43R16800A-5TL

Package 66-pin TSOP-II 66-pin TSOP-II, Lead-free

Integrated Silicon Solution, Inc. 1-800-379-4774
07/11/05

PACKAGING INFORMATION

Plastic TSOP 66-pin Package Code T Type II

N/2+1 E1 E

Notes Controlling dimension millimieters,
unless otherwise specified. BSC = Basic lead spacing between
centers. Dimensions D and E1 do not include
mold flash protrusions and should be measured from the bottom of the package. Formed leads shall be planar with respect to one another within inches at the seating plane.

SEATING PLANE

Plastic TSOP T - Type II

Millimeters

Inches

Symbol Min Max Min Max

Ref. Std.

No. Leads N

ZD REF
0° 8°
0° 8°

Integrated Silicon Solution, Inc. 1-800-379-4774
08/09/05

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IS43R16800A-5TL-TR Datasheet file may be downloaded here without warranties.

Datasheet ID: IS43R16800A-5TL-TR 639300