IS42SM16200C-75BLI-TR

IS42SM16200C-75BLI-TR Datasheet

IS42SM16200C IS42RM16200C IS42VM16200C

Part	Datasheet
IS42SM16200C-75BLI-TR	IS42SM16200C-75BLI-TR (pdf)

Related Parts	Information
IS42SM16200C-75BLI	IS42SM16200C-75BLI
IS42VM16200C-75BLI	IS42VM16200C-75BLI
IS42VM16200C-75BLI-TR	IS42VM16200C-75BLI-TR
IS42RM16200C-75BLI	IS42RM16200C-75BLI
IS42RM16200C-75BLI-TR	IS42RM16200C-75BLI-TR

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IS42SM16200C IS42RM16200C IS42VM16200C 1M x 16Bits x 2Banks Low Power Synchronous DRAM These IS42SM/RM/VM16200C are low power 33,554,432 bits CMOS Synchronous DRAM organized as 2 banks of 1,048,576 words x 16 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve high bandwidth. All input and output voltage levels are compatible with LVCMOS. • JEDEC standard 3.3V, 2.5V, 1.8V power supply. • Auto refresh and self refresh. • All pins are compatible with LVCMOS interface. • 4K refresh cycle / 64ms. • Programmable Burst Length and Burst Type. - 1, 2, 4, 8 or Full Page for Sequential Burst. - 4 or 8 for Interleave Burst. • Programmable CAS Latency 2,3 clocks. • Programmable Driver Strength Control - Full Strength or 1/2, 1/4, 1/8 of Full Strength • Deep Power Down Mode. • All inputs and outputs referenced to the positive edge of the system clock. • Data mask function by DQM. • Internal dual banks operation. • Burst Read Single Write operation. • Special Function Support. - PASR Partial Array Self Refresh - Auto TCSR Temperature Compensated Self Refresh • Automatic precharge, includes CONCURRENT Auto Precharge Mode and controlled Precharge. Copyright 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a. the risk of injury or damage has been minimized; b. the user assume all such risks and c. potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances IS42SM/RM/VM16200C Figure1 54Ball FBGA Ball Assignment 3 456 7 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSS UDQM CLK CKE VSS A5 VDDQ DQ0 VDD VSSQ DQ2 DQ1 VDDQ DQ4 DQ3 VSSQ DQ6 DQ5 VDD LDQM DQ7 /CAS /RAS /WE A1 A10 A2 VDD [Top View] Table2 Pin Descriptions Pin Pin Name System Clock Clock Enable Chip Select Bank Address A0~A10 /RAS, /CAS, /WE LDQM,UDQM DQ0~DQ15 VDD/VSS VDDQ/VSSQ NC Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table Table 3 Burst Definition Starting Column Order of Access Within a Burst Burst Address Length A2 A1 A0 Sequential Interleaved 0-1-2-3 0-1-2-3 1-2-3-0 1-0-3-2 2-3-0-1 2-3-0-1 3-0-1-2 3-2-1-0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 Full Page n=A0-8 Location 0-511 Cn, Cn+1. Cn+2, Cn+3, Cn... Not Supported Note For full-page accesses y = 512 For a burst length of two, A1-A8 select the block- of-two burst A0 selects the starting column within the block. For a burst length of four, A2-A8 select the blockof-four burst A0-A1 select the starting column within the block. For a burst length of eight, A3-A8 select the block-of-eight burst A0-A2 select the starting column within the block. For a full-page burst, the full row is selected and A0-A8 select the starting column. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. For a burst length of one, A0-A8 select the unique column to be accessed, and mode register bit M3 is ignored. IS42SM/RM/VM16200C Figure5 Extended Mode Register BA A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 11 10 TCSR PASR Extended Mode Register Ex E6 E5 Driver Strength Full Strength 1/2 Strength 1/4 Strength 1/8 Strength Maximum Case Temp. Ordering Information VDD = 1.8V Industrial Range -40oC to +85oC Configuration 2Mx16 Frequency MHz Speed ns Order Part No. IS42VM16200C-6BLI IS42VM16200C-75BLI Package 54-ball BGA, Lead-free 54-ball BGA, Lead-free Ordering Information VDD = 2.5V Industrial Range -40oC to +85oC Configuration 2Mx16 Frequency MHz Speed ns Order Part No. IS42RM16200C-6BLI IS42RM16200C-75BLI Package 54-ball BGA, Lead-free 54-ball BGA, Lead-free Ordering Information VDD = 3.3V Industrial Range -40oC to +85oC Configuration 2Mx16 Frequency MHz Speed ns Order Part No. IS42SM16200C-6BLI IS42SM16200C-75BLI Package 54-ball BGA, Lead-free 54-ball BGA, Lead-free

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IS42SM16200C IS42RM16200C IS42VM16200C
1M x 16Bits x 2Banks Low Power Synchronous DRAM

These IS42SM/RM/VM16200C are low power 33,554,432 bits CMOS Synchronous DRAM organized as 2 banks of 1,048,576 words x 16 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve high bandwidth. All input and output voltage levels are compatible with LVCMOS.
• JEDEC standard 3.3V, 2.5V, 1.8V power supply.
• Auto refresh and self refresh.
• All pins are compatible with LVCMOS interface.
• 4K refresh cycle / 64ms.
• Programmable Burst Length and Burst Type.
- 1, 2, 4, 8 or Full Page for Sequential Burst. - 4 or 8 for Interleave Burst.
• Programmable CAS Latency 2,3 clocks.
• Programmable Driver Strength Control - Full Strength or 1/2, 1/4, 1/8 of Full Strength
• Deep Power Down Mode.
• All inputs and outputs referenced to the positive edge of the system clock.
• Data mask function by DQM.
• Internal dual banks operation.
• Burst Read Single Write operation.
• Special Function Support.
- PASR Partial Array Self Refresh - Auto TCSR Temperature Compensated Self Refresh
• Automatic precharge, includes CONCURRENT Auto Precharge Mode and controlled Precharge.

Copyright 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a. the risk of injury or damage has been minimized;
b. the user assume all such risks and
c. potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

IS42SM/RM/VM16200C

Figure1 54Ball FBGA Ball Assignment
3 456 7

VSS DQ15 VSSQ

DQ14 DQ13 VDDQ

DQ12 DQ11 VSSQ

DQ10 DQ9 VDDQ

DQ8 NC VSS

UDQM CLK CKE

VSS A5

VDDQ DQ0 VDD

VSSQ DQ2 DQ1

VDDQ DQ4 DQ3

VSSQ DQ6 DQ5

VDD LDQM DQ7
/CAS /RAS /WE

A1 A10

A2 VDD
[Top View]

Table2 Pin Descriptions Pin

Pin Name

System Clock

Clock Enable

Chip Select

Bank Address

A0~A10
/RAS, /CAS, /WE

LDQM,UDQM DQ0~DQ15 VDD/VSS VDDQ/VSSQ NC
Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table

Table 3 Burst Definition

Starting Column Order of Access Within a Burst

Burst

Address

Length A2

A1 A0

Sequential

Interleaved
0-1-2-3
0-1-2-3
1-2-3-0
1-0-3-2
2-3-0-1
2-3-0-1
3-0-1-2
3-2-1-0
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Full Page
n=A0-8 Location 0-511

Cn, Cn+1. Cn+2, Cn+3, Cn...

Not Supported

Note For full-page accesses y = 512 For a burst length of two, A1-A8 select the block-
of-two burst A0 selects the starting column within the block. For a burst length of four, A2-A8 select the blockof-four burst A0-A1 select the starting column within the block. For a burst length of eight, A3-A8 select the block-of-eight burst A0-A2 select the starting column within the block. For a full-page burst, the full row is selected and A0-A8 select the starting column. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. For a burst length of one, A0-A8 select the unique column to be accessed, and mode register bit M3 is ignored.

IS42SM/RM/VM16200C

Figure5 Extended Mode Register

BA A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
11 10

TCSR

PASR

Extended Mode Register Ex

E6 E5

Driver Strength Full Strength 1/2 Strength 1/4 Strength 1/8 Strength

Maximum Case Temp.
Ordering Information VDD = 1.8V Industrial Range -40oC to +85oC

Configuration 2Mx16

Frequency MHz

Speed ns

Order Part No. IS42VM16200C-6BLI

IS42VM16200C-75BLI

Package 54-ball BGA, Lead-free 54-ball BGA, Lead-free
Ordering Information VDD = 2.5V Industrial Range -40oC to +85oC

Configuration 2Mx16

Frequency MHz

Speed ns

Order Part No. IS42RM16200C-6BLI

IS42RM16200C-75BLI

Package 54-ball BGA, Lead-free 54-ball BGA, Lead-free
Ordering Information VDD = 3.3V Industrial Range -40oC to +85oC

Configuration 2Mx16

Frequency MHz

Speed ns

Order Part No. IS42SM16200C-6BLI

IS42SM16200C-75BLI

Package 54-ball BGA, Lead-free 54-ball BGA, Lead-free

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IS42SM16200C-75BLI-TR Datasheet file may be downloaded here without warranties.

Datasheet ID: IS42SM16200C-75BLI-TR 639298