IS42S16160B-6BLI-TR

IS42S16160B-6BLI-TR Datasheet

IS42S83200B IS42S16160B

Part	Datasheet
IS42S16160B-6BLI-TR	IS42S16160B-6BLI-TR (pdf)

Related Parts	Information
IS42S16160B-7TLI-TR	IS42S16160B-7TLI-TR
IS42S16160B-7BI-TR	IS42S16160B-7BI-TR
IS42S16160B-6B	IS42S16160B-6B
IS42S16160B-6B-TR	IS42S16160B-6B-TR
IS42S16160B-7TL	IS42S16160B-7TL
IS42S16160B-6BL	IS42S16160B-6BL
IS42S16160B-6BL-TR	IS42S16160B-6BL-TR
IS42S83200B-7TLI-TR	IS42S83200B-7TLI-TR
IS42S16160B-6T	IS42S16160B-6T
IS42S16160B-6T-TR	IS42S16160B-6T-TR
IS42S83200B-7TLI	IS42S83200B-7TLI
IS42S83200B-7TL-TR	IS42S83200B-7TL-TR
IS42S83200B-7TL	IS42S83200B-7TL
IS42S16160B-7BLI	IS42S16160B-7BLI
IS42S16160B-7TLI	IS42S16160B-7TLI
IS42S16160B-7TL-TR	IS42S16160B-7TL-TR
IS42S16160B-7TI-TR	IS42S16160B-7TI-TR
IS42S16160B-7TI	IS42S16160B-7TI
IS42S16160B-7T-TR	IS42S16160B-7T-TR
IS42S16160B-7B-TR	IS42S16160B-7B-TR
IS42S16160B-7BLI-TR	IS42S16160B-7BLI-TR
IS42S16160B-6TL	IS42S16160B-6TL
IS42S16160B-7BL-TR	IS42S16160B-7BL-TR
IS42S16160B-7BL	IS42S16160B-7BL
IS42S16160B-7BI	IS42S16160B-7BI
IS42S83200B-7TI-TR	IS42S83200B-7TI-TR
IS42S16160B-7B	IS42S16160B-7B
IS42S16160B-6TL-TR	IS42S16160B-6TL-TR
IS42S16160B-7T	IS42S16160B-7T
IS42S83200B-7T-TR	IS42S83200B-7T-TR
IS42S83200B-6TL	IS42S83200B-6TL
IS42S83200B-6T	IS42S83200B-6T
IS42S83200B-7T	IS42S83200B-7T
IS42S83200B-6T-TR	IS42S83200B-6T-TR
IS42S83200B-7TI	IS42S83200B-7TI
IS42S83200B-6TL-TR	IS42S83200B-6TL-TR
IS42S16160B-6TLI	IS42S16160B-6TLI
IS42S83200B-6TLI	IS42S83200B-6TLI
IS42S83200B-6TLI-TR	IS42S83200B-6TLI-TR
IS42S16160B-6TLI-TR	IS42S16160B-6TLI-TR
IS42S16160B-6BLI	IS42S16160B-6BLI

PDF Datasheet Preview
IS42S83200B IS42S16160B 32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM SEPTEMBER 2008 • Clock frequency 166, 143, 133 MHz • Fully synchronous all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply IS42S83200B VDD VDDQ 3.3V 3.3V IS42S16160B 3.3V 3.3V • LVTTL interface • Programmable burst length 1, 2, 4, 8, full page • Programmable burst sequence Sequential/Interleave • Auto Refresh CBR • Self Refresh • 8K refresh cycles every 64 ms • Random column address every clock cycle • Programmable CAS latency 2, 3 clocks • Burst read/write and burst read/single write operations capability • Burst termination by burst stop and precharge command • Available in Industrial Temperature • Available in 54-pin TSOP-II and 54-ball BGA x16 only • Available in Lead-free OVERVIEW ISSI's 256Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 256Mb SDRAM is organized as follows. IS42S83200B IS42S16160B 8M x 8 x 4 Banks 4M x16x4 Banks 54-pin TSOPII 54-pin TSOPII 54-ball BGA KEY TIMING PARAMETERS Parameter Unit Clk Cycle Time CAS Latency = 3 CAS Latency = 2 Clk Frequency CAS Latency = 3 CAS Latency = 2 166 143 125 100 Access Time from Clock CAS Latency = 3 CAS Latency = 2 The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in BURST DEFINITION table. BURST DEFINITION Burst Starting Column Length Address A1 A0 A2 A1 A0 Full n=A0-A8 x16 Page n = A0-A9 x8 y location0-y Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn + 1, Cn + 2 Cn + 3, Cn + 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not Supported Integrated Silicon Solution, Inc. 07/28/08 IS42S83200B, IS42S16160B CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier n + m - 1 , and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in CAS Latency diagrams. The Allowable Operating Frequency table indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Operating Mode The normal operating mode is selected by setting M7 and M8 to zero the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location nonburst accesses. CAS Latency Allowable Operating Frequency MHz Speed CAS Latency = 2 CAS Latency = 3 CAS LATENCY COMMAND DQ READ DOUT CAS Latency - 2 T0 CLK COMMAND READ NOP tAC ORDERING INFORMATION - VDD = 3.3V Commercial Range 0°C to 70°C Frequency 166 MHz 143 MHz Speed ns 6 7 Order Part No. IS42S83200B-6T IS42S83200B-7T Package 54-Pin TSOPII 54-Pin TSOPII Frequency 166 MHz 143 MHz 143 MHz Speed ns 6 7 Order Part No. IS42S16160B-6T IS42S16160B-7T IS42S16160B-7B Package 54-Pin TSOPII 54-Pin TSOPII 54-ball BGA ORDERING INFORMATION - VDD = 3.3V Industrial Range -40°C to 85°C Frequency 143 MHz Speed ns Order Part No. Package IS42S83200B-7TI 54-Pin TSOPII Frequency 143 MHz 143 MHz Speed ns 7 Order Part No. IS42S16160B-7TI IS42S16160B-7BI Package 54-Pin TSOPII 54-ball BGA Integrated Silicon Solution, Inc. 07/28/08 IS42S83200B, IS42S16160B ORDERING INFORMATION - VDD = 3.3V Commercial Range 0°C to 70°C Frequency 166 MHz 143 MHz Speed ns 6 7 Order Part No. IS42S83200B-6TL IS42S83200B-7TL Package 54-Pin TSOPII, Lead-free 54-Pin TSOPII, Lead-free Frequency 166 MHz 166 MHz 143 MHz 143 MHz 143 MHz Speed ns 6 7 Order Part No. IS42S16160B-6TL IS42S16160B-6BL IS42S16160B-7TL IC42S16160B-7TL IS42S16160B-7BL Package 54-Pin TSOPII, Lead-free 54-ball fBGA, Lead-free 54-Pin TSOPII, Lead-free 54-Pin TSOPII, Lead-free 54-ball fBGA, Lead-free ORDERING INFORMATION - VDD = 3.3V Industrial Range -40°C to 85°C Frequency 166 MHz 143 MHz Speed ns 6 7 Order Part No. IS42S83200B-6TLI IS42S83200B-7TLI Package 54-Pin TSOPII, Lead-free 54-Pin TSOPII, Lead-free Frequency 166 MHz 166 MHz 143 MHz 143 MHz Speed ns 6 7 Order Part No. IS42S16160B-6TLI IS42S16160B-6BLI IS42S16160B-7TLI IS42S16160B-7BLI Package 54-Pin TSOPII, Lead-free 54-ball fBGA, Lead-free 54-Pin TSOPII, Lead-free 54-ball fBGA, Lead-free Integrated Silicon Solution, Inc. 07/28/08 NOTE : CONTROLLING DIMENSION MM Reference document JEDEC MO-207 08/14/2008 PACKAGING INFORMATION Plastic TSOP 86-Pin Package Code T Type II N/2+1 E1 E Notes Controlling dimension millimieters, unless otherwise specified. BSC = Basic lead spacing between centers. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. Formed leads shall be planar with respect to one another within inches at the seating plane. SEATING PLANE Plastic TSOP T - Type II Millimeters Inches Symbol Min Max Min Max Ref. Std. No. Leads N ZD REF 0° 8° 0° 8° Integrated Silicon Solution, Inc. Plastic TSOP T - Type II Millimeters Inches Symbol Min Max Min Max Ref. Std. No. Leads N ZD REF 0° 8° 0° 8°

PDF Datasheet Preview

IS42S83200B IS42S16160B
32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM

SEPTEMBER 2008
• Clock frequency 166, 143, 133 MHz
• Fully synchronous all signals referenced to a positive clock edge
• Internal bank for hiding row access/precharge
• Power supply

IS42S83200B

VDD VDDQ 3.3V 3.3V

IS42S16160B
3.3V 3.3V
• LVTTL interface
• Programmable burst length 1, 2, 4, 8, full page
• Programmable burst sequence Sequential/Interleave
• Auto Refresh CBR
• Self Refresh
• 8K refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency 2, 3 clocks
• Burst read/write and burst read/single write operations capability
• Burst termination by burst stop and precharge command
• Available in Industrial Temperature
• Available in 54-pin TSOP-II and 54-ball BGA x16 only
• Available in Lead-free

OVERVIEW

ISSI's 256Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 256Mb SDRAM is organized as follows.

IS42S83200B

IS42S16160B
8M x 8 x 4 Banks 4M x16x4 Banks
54-pin TSOPII 54-pin TSOPII
54-ball BGA

KEY TIMING PARAMETERS

Parameter

Unit

Clk Cycle Time CAS Latency = 3 CAS Latency = 2

Clk Frequency CAS Latency = 3 CAS Latency = 2
166 143
125 100

Access Time from Clock

CAS Latency = 3

CAS Latency = 2
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in BURST DEFINITION table.

BURST DEFINITION

Burst

Starting Column

Length

Address

A1 A0

A2 A1 A0

Full n=A0-A8 x16 Page n = A0-A9 x8 y location0-y

Order of Accesses Within a Burst

Type = Sequential

Type = Interleaved
0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2
0-1-2-3 1-0-3-2-3-0-1 3-2-1-0
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn + 1, Cn + 2 Cn + 3, Cn +
0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not Supported

Integrated Silicon Solution, Inc.
07/28/08

IS42S83200B, IS42S16160B

CAS Latency

The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier n + m - 1 , and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in CAS Latency diagrams. The Allowable Operating Frequency table indicates the operating frequencies at which each CAS latency setting can be used.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Operating Mode

The normal operating mode is selected by setting M7 and M8 to zero the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts.

Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location nonburst accesses.

CAS Latency

Allowable Operating Frequency MHz

Speed

CAS Latency = 2

CAS Latency = 3

CAS LATENCY

COMMAND DQ

READ

DOUT

CAS Latency - 2

T0 CLK

COMMAND READ

NOP tAC
ORDERING INFORMATION - VDD = 3.3V Commercial Range 0°C to 70°C

Frequency 166 MHz 143 MHz

Speed ns 6 7

Order Part No. IS42S83200B-6T IS42S83200B-7T

Package 54-Pin TSOPII 54-Pin TSOPII

Frequency 166 MHz 143 MHz 143 MHz

Speed ns 6 7

Order Part No. IS42S16160B-6T IS42S16160B-7T IS42S16160B-7B

Package 54-Pin TSOPII 54-Pin TSOPII
54-ball BGA
ORDERING INFORMATION - VDD = 3.3V Industrial Range -40°C to 85°C

Frequency 143 MHz

Speed ns Order Part No.

Package

IS42S83200B-7TI 54-Pin TSOPII

Frequency 143 MHz 143 MHz

Speed ns 7

Order Part No. IS42S16160B-7TI IS42S16160B-7BI

Package 54-Pin TSOPII
54-ball BGA

Integrated Silicon Solution, Inc.
07/28/08

IS42S83200B, IS42S16160B
ORDERING INFORMATION - VDD = 3.3V Commercial Range 0°C to 70°C

Frequency 166 MHz 143 MHz

Speed ns 6 7

Order Part No. IS42S83200B-6TL IS42S83200B-7TL

Package 54-Pin TSOPII, Lead-free 54-Pin TSOPII, Lead-free

Frequency 166 MHz 166 MHz 143 MHz 143 MHz 143 MHz

Speed ns 6 7

Order Part No. IS42S16160B-6TL IS42S16160B-6BL IS42S16160B-7TL IC42S16160B-7TL IS42S16160B-7BL

Package 54-Pin TSOPII, Lead-free 54-ball fBGA, Lead-free 54-Pin TSOPII, Lead-free 54-Pin TSOPII, Lead-free 54-ball fBGA, Lead-free
ORDERING INFORMATION - VDD = 3.3V Industrial Range -40°C to 85°C

Frequency 166 MHz 143 MHz

Speed ns 6 7

Order Part No. IS42S83200B-6TLI IS42S83200B-7TLI

Package 54-Pin TSOPII, Lead-free 54-Pin TSOPII, Lead-free

Frequency 166 MHz 166 MHz 143 MHz 143 MHz

Speed ns 6 7

Order Part No. IS42S16160B-6TLI IS42S16160B-6BLI IS42S16160B-7TLI IS42S16160B-7BLI

Package 54-Pin TSOPII, Lead-free 54-ball fBGA, Lead-free 54-Pin TSOPII, Lead-free 54-ball fBGA, Lead-free

Integrated Silicon Solution, Inc.
07/28/08

NOTE :

CONTROLLING DIMENSION MM Reference document JEDEC MO-207
08/14/2008

PACKAGING INFORMATION

Plastic TSOP 86-Pin Package Code T Type II

N/2+1 E1 E

Notes Controlling dimension millimieters,
unless otherwise specified. BSC = Basic lead spacing between
centers. Dimensions D and E1 do not include
mold flash protrusions and should be measured from the bottom of the package. Formed leads shall be planar with respect to one another within inches at the seating plane.

SEATING PLANE

Plastic TSOP T - Type II

Millimeters

Inches

Symbol Min Max Min Max

Ref. Std.

No. Leads N

ZD REF
0° 8°
0° 8°

Integrated Silicon Solution, Inc.

Plastic TSOP T - Type II

Millimeters

Inches

Symbol Min Max Min Max

Ref. Std.

No. Leads N

ZD REF
0° 8°
0° 8°

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Datasheet ID: IS42S16160B-6BLI-TR 639296