IS42S32800B-7TL

IS42S32800B-7TL Datasheet

IS42S32800B

Part	Datasheet
IS42S32800B-7TL	IS42S32800B-7TL (pdf)

Related Parts	Information
IS42S32800B-7BI	IS42S32800B-7BI
IS42S32800B-7B-TR	IS42S32800B-7B-TR
IS42S32800B-7BI-TR	IS42S32800B-7BI-TR
IS42S32800B-7BL-TR	IS42S32800B-7BL-TR
IS42S32800B-7BLI	IS42S32800B-7BLI
IS42S32800B-7BLI-TR	IS42S32800B-7BLI-TR
IS42S32800B-7B	IS42S32800B-7B
IS42S32800B-7T-TR	IS42S32800B-7T-TR
IS42S32800B-7TI	IS42S32800B-7TI
IS42S32800B-7TI-TR	IS42S32800B-7TI-TR
IS42S32800B-7TL-TR	IS42S32800B-7TL-TR
IS42S32800B-7TLI	IS42S32800B-7TLI
IS42S32800B-7TLI-TR	IS42S32800B-7TLI-TR
IS42S32800B-7T	IS42S32800B-7T
IS42S32800B-7BL	IS42S32800B-7BL
IS42S32800B-6B-TR	IS42S32800B-6B-TR
IS42S32800B-6TL-TR	IS42S32800B-6TL-TR
IS42S32800B-6TL	IS42S32800B-6TL
IS42S32800B-6T-TR	IS42S32800B-6T-TR
IS42S32800B-6T	IS42S32800B-6T
IS42S32800B-6BL-TR	IS42S32800B-6BL-TR
IS42S32800B-6BL	IS42S32800B-6BL
IS42S32800B-6B	IS42S32800B-6B
IS42S32800B-6BI-TR	IS42S32800B-6BI-TR
IS42S32800B-6BLI	IS42S32800B-6BLI
IS42S32800B-6TLI-TR	IS42S32800B-6TLI-TR
IS42S32800B-6BI	IS42S32800B-6BI
IS42S32800B-6TLI	IS42S32800B-6TLI
IS42S32800B-6BLI-TR	IS42S32800B-6BLI-TR

PDF Datasheet Preview
IS42S32800B 2M Words x 32 Bits x 4 Banks 256-MBIT SYNCHRONOUS DYNAMIC RAM JULY 2009 • Concurrent auto precharge • Clock rate:166/143 MHz • Fully synchronous operation • Internal pipelined architecture • Four internal banks 2M x 32bit x 4bank • Programmable Mode -CAS#Latency:2 or 3 -Burst Length:1,2,4,8,or full page -Burst Type:interleaved or linear burst -Burst-Read-Single-Write • Burst stop function • Individual byte controlled by DQM0-3 • Auto Refresh and Self Refresh • 4096 refresh cycles/64ms 15.6µs/row • 4096 refresh cycles/32ms for industrial grade • Single +3.3V ±0.3V power supply • Interface:LVTTL • Package 86 Pin TSOP-2,0.50mm Pin Pitch 8x13mm, 90 Ball LF-BGA, Ball pitch 0.8mm • Pb-free package is available. The ISSI IS42S32800B is a high-speed CMOS configured as a quad 2M x 32 DRAM with a synchronous interface all signals are registered on the positive edge of the clock signal,CLK . Each of the 2M x 32 bit banks is organized as 4096 rows by 512 columns by 32 bits.Read and write accesses start at a selected locations in a programmed sequence. Accesses begin with the registration of a BankActive command which is then followed by a Read or Write command The ISSI IS42S32800B provides for programmable Read or Write burst lengths of 1,2,4,8,or full page, with a burst termination operation. An auto precharge function may be enable to provide a self-timed row precharge that is initiated at the end of the burst sequence.The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register,the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth. Integrated Silicon Solution, Inc. 07/21/09 IS42S32800B FUNCTIONAL BLOCK DIAGRAM CS# RAS# CAS# WE# CLOCK BUFFER COMMAND DECODER A10/AP COLUMN C O U N TE R CONTROL SIGNAL G E N E R AT O R MODE REGISTER A9 A 11 BS0 BS1 ADDRESS BUFFER REFRESH COUNTER DQ0 D Q 31 DQ BUFFER DQM0~3 Row Decoder Row Decoder Row Decoder Row Decoder Column Decoder 4096 X 512 X 32 CELL ARRAY BANK #0 Sense Amplifier Sense Amplifier 4096 X 512 X 32 CELL ARRAY BANK #1 Col um n Decoder Column Decoder 4096 X 512 X 32 CELL ARRAY BANK #2 Sense Amplifier Sense Amplifier 4096 X 512 X 32 CELL ARRAY BANK #3 Column Decoder ORDERING INFORMATION Commercial Range 0°C to +70°C Frequency 166 MHz 166 MHz 166 MHz 166 MHz 143 MHz 143 MHz 143 MHz 143 MHz Speed ns 6 7 Order Part No. IS42S32800B-6T IS42S32800B-6TL IS42S32800B-6B IS42S32800B-6BL IS42S32800B-7T IS42S32800B-7TL IS42S32800B-7B IS42S32800B-7BL Package 400 mil TSOP-II 400 mil TSOP-II, Lead-free 8 x13mm BGA 8 x13mm BGA, Lead-free 400 mil TSOP-II 400 mil TSOP-II, Lead-free 8 x13mm BGA 8 x13mm BGA, Lead-free Industrial Range -40°C to +85°C Frequency Speed ns 166 MHz 166 MHz 166 MHz 166 MHz 143 MHz 143 MHz 143 MHz 143 MHz Order Part No. IS42S32800B-6TI IS42S32800B-6TLI IS42S32800B-6BI IS42S32800B-6BLI IS42S32800B-7TI IS42S32800B-7TLI IS42S32800B-7BI IS42S32800B-7BLI Package 400 mil TSOP-II 400 mil TSOP-II, Lead-free 8 x13mm BGA 8 x13mm BGA, Lead-free 400 mil TSOP-II 400 mil TSOP-II, Lead-free 8 x13mm BGA 8 x13mm BGA, Lead-free Integrated Silicon Solution, Inc. 07/21/09 Integrated Silicon Solution, Inc. NOTE : Controlling dimension mm Dimension D and E1 do not include mold protrusion Dimension b does not include dambar protrusion/intrusion. Formed leads shall be planar with respect to one another within 0.1mm at the seating plane after final test. IS42S32800B 09/26/2006 07/21/09 07/21/09 Integrated Silicon Solution, Inc. IS42S32800B D1 NOTE : CONTROLLING DIMENSION MM Reference document JEDEC MO-207 08/14/2008

PDF Datasheet Preview

IS42S32800B
2M Words x 32 Bits x 4 Banks 256-MBIT SYNCHRONOUS DYNAMIC RAM

JULY 2009
• Concurrent auto precharge
• Clock rate:166/143 MHz
• Fully synchronous operation
• Internal pipelined architecture
• Four internal banks 2M x 32bit x 4bank
• Programmable Mode
-CAS#Latency:2 or 3 -Burst Length:1,2,4,8,or full page -Burst Type:interleaved or linear burst -Burst-Read-Single-Write
• Burst stop function
• Individual byte controlled by DQM0-3
• Auto Refresh and Self Refresh
• 4096 refresh cycles/64ms 15.6µs/row
• 4096 refresh cycles/32ms for industrial grade
• Single +3.3V ±0.3V power supply
• Interface:LVTTL
• Package 86 Pin TSOP-2,0.50mm Pin Pitch
8x13mm, 90 Ball LF-BGA, Ball pitch 0.8mm
• Pb-free package is available.

The ISSI IS42S32800B is a high-speed CMOS configured as a quad 2M x 32 DRAM with a synchronous interface all signals are registered on the positive edge of the clock signal,CLK .

Each of the 2M x 32 bit banks is organized as 4096 rows by 512 columns by 32 bits.Read and write accesses start at a selected locations in a programmed sequence. Accesses begin with the registration of a BankActive command which is then followed by a Read or Write command

The ISSI IS42S32800B provides for programmable Read or Write burst lengths of 1,2,4,8,or full page, with a burst termination operation. An auto precharge function may be enable to provide a self-timed row precharge that is initiated at the end of the burst sequence.The refresh functions, either Auto or Self Refresh are easy to use.

By having a programmable mode register,the system can choose the most suitable modes to maximize its performance.

These devices are well suited for applications requiring high memory bandwidth.

Integrated Silicon Solution, Inc.
07/21/09

IS42S32800B

FUNCTIONAL BLOCK DIAGRAM

CS# RAS# CAS# WE#

CLOCK BUFFER

COMMAND DECODER

A10/AP

COLUMN C O U N TE R

CONTROL SIGNAL

G E N E R AT O R

MODE REGISTER

A9 A 11 BS0 BS1

ADDRESS BUFFER

REFRESH COUNTER

DQ0 D Q 31

DQ BUFFER

DQM0~3

Row Decoder

Row Decoder

Row Decoder

Row Decoder

Column Decoder 4096 X 512 X 32 CELL ARRAY BANK #0 Sense Amplifier

Sense Amplifier 4096 X 512 X 32

CELL ARRAY BANK #1

Col um n Decoder

Column Decoder 4096 X 512 X 32 CELL ARRAY BANK #2 Sense Amplifier

Sense Amplifier 4096 X 512 X 32

CELL ARRAY BANK #3

Column Decoder
ORDERING INFORMATION

Commercial Range 0°C to +70°C

Frequency 166 MHz 166 MHz 166 MHz 166 MHz 143 MHz 143 MHz 143 MHz 143 MHz

Speed ns 6 7

Order Part No. IS42S32800B-6T IS42S32800B-6TL IS42S32800B-6B IS42S32800B-6BL IS42S32800B-7T IS42S32800B-7TL IS42S32800B-7B IS42S32800B-7BL

Package 400 mil TSOP-II 400 mil TSOP-II, Lead-free 8 x13mm BGA 8 x13mm BGA, Lead-free 400 mil TSOP-II 400 mil TSOP-II, Lead-free 8 x13mm BGA 8 x13mm BGA, Lead-free

Industrial Range -40°C to +85°C

Frequency

Speed ns
166 MHz
166 MHz
166 MHz
166 MHz
143 MHz
143 MHz
143 MHz
143 MHz

Order Part No. IS42S32800B-6TI IS42S32800B-6TLI IS42S32800B-6BI IS42S32800B-6BLI IS42S32800B-7TI IS42S32800B-7TLI IS42S32800B-7BI IS42S32800B-7BLI

Package 400 mil TSOP-II 400 mil TSOP-II, Lead-free 8 x13mm BGA 8 x13mm BGA, Lead-free 400 mil TSOP-II 400 mil TSOP-II, Lead-free 8 x13mm BGA 8 x13mm BGA, Lead-free

Integrated Silicon Solution, Inc.
07/21/09

Integrated Silicon Solution, Inc.

NOTE :

Controlling dimension mm

Dimension D and E1 do not include mold protrusion

Dimension b does not include dambar protrusion/intrusion.

Formed leads shall be planar with respect to one another within 0.1mm
at the seating plane after final test.

IS42S32800B
09/26/2006
07/21/09
07/21/09

Integrated Silicon Solution, Inc.

IS42S32800B D1

NOTE :

CONTROLLING DIMENSION MM Reference document JEDEC MO-207
08/14/2008

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IS42S32800B-7TL Datasheet file may be downloaded here without warranties.

Datasheet ID: IS42S32800B-7TL 639294