IS42S32400B-7TI-TR

IS42S32400B-7TI-TR Datasheet

IS42S32400B

Part	Datasheet
IS42S32400B-7TI-TR	IS42S32400B-7TI-TR (pdf)

Related Parts	Information
IS42S32400B-7TLI-TR	IS42S32400B-7TLI-TR
IS42S32400B-7TI	IS42S32400B-7TI
IS42S32400B-7BLI-TR	IS42S32400B-7BLI-TR
IS42S32400B-6TL-TR	IS42S32400B-6TL-TR
IS42S32400B-7BLI	IS42S32400B-7BLI
IS42S32400B-7T-TR	IS42S32400B-7T-TR
IS42S32400B-7T	IS42S32400B-7T
IS42S32400B-7BL	IS42S32400B-7BL
IS42S32400B-6B	IS42S32400B-6B
IS42S32400B-6TL	IS42S32400B-6TL
IS42S32400B-6T-TR	IS42S32400B-6T-TR
IS42S32400B-6T	IS42S32400B-6T
IS42S32400B-6BL-TR	IS42S32400B-6BL-TR
IS42S32400B-7BL-TR	IS42S32400B-7BL-TR
IS42S32400B-6B-TR	IS42S32400B-6B-TR
IS42S32400B-7BI-TR	IS42S32400B-7BI-TR
IS42S32400B-7TL	IS42S32400B-7TL
IS42S32400B-7B	IS42S32400B-7B
IS42S32400B-7TL-TR	IS42S32400B-7TL-TR
IS42S32400B-7B-TR	IS42S32400B-7B-TR
IS42S32400B-7TLI	IS42S32400B-7TLI
IS42S32400B-7BI	IS42S32400B-7BI
IS42S32400B-6BL	IS42S32400B-6BL
IS45S32400B-6TLA1	IS45S32400B-6TLA1
IS45S32400B-6TLA1-TR	IS45S32400B-6TLA1-TR
IS45S32400B-7BLA1-TR	IS45S32400B-7BLA1-TR
IS45S32400B-7TLA1	IS45S32400B-7TLA1
IS45S32400B-7TLA1-TR	IS45S32400B-7TLA1-TR
IS45S32400B-7BLA1	IS45S32400B-7BLA1
IS45S32400B-6BLA1	IS45S32400B-6BLA1
IS45S32400B-6BLA1-TR	IS45S32400B-6BLA1-TR

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IS42S32400B 4Meg x 32 128-MBIT SYNCHRONOUS DRAM PRELIMINARY INFORMATION MARCH 2009 • Clock frequency 166, 143, 125, 100 MHz • Fully synchronous all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply IS42S32400B VDD VDDQ 3.3V 3.3V • LVTTL interface • Programmable burst length 1, 2, 4, 8, full page • Programmable burst sequence Sequential/Interleave • Auto Refresh CBR • Self Refresh with programmable refresh periods • 4096 refresh cycles every 64 ms • Random column address every clock cycle • Programmable CAS latency 2, 3 clocks • Burst read/write and burst read/single write operations capability • Burst termination by burst stop and precharge command • Available in Industrial Temperature • Available in 86-pin TSOP-II and 90-ball FBGA • Available in Lead-free OVERVIEW ISSI's 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. KEY TIMING PARAMETERS Parameter Unit Clk Cycle Time CAS Latency = 3 CAS Latency = 2 Clk Frequency CAS Latency = 3 CAS Latency = 2 166 143 125 100 Access Time from Clock CAS Latency = 3 CAS Latency = 2 Copyright 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. 1-800-379-4774 03/03/09 IS42S32400B DEVICE OVERVIEW The 128Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V VDD and 3.3V VDDQ memory systems containing 134,217,728 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 33,554,432-bit bank is organized as 4,096 rows by 256 columns by 32 bits. The 128Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in BURST DEFINITION table. BURST DEFINITION Burst Length Full Page y Starting Column Address A1 A0 A2 A1 A0 n = A0-A7 location 0-y Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn + 1, Cn + 2 Cn + 3, Cn + 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not Supported Integrated Silicon Solution, Inc. 1-800-379-4774 IS42S32400B CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier n + m - 1 , and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in CAS Latency diagrams. The Allowable Operating Frequency table indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Operating Mode The normal operating mode is selected by setting M7 and M8 to zero the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location nonburst accesses. CAS Latency Allowable Operating Frequency MHz Speed CAS Latency = 2 CAS Latency = 3 CAS LATENCY COMMAND DQ READ DOUT CAS Latency - 2 T0 CLK COMMAND READ NOP tAC ORDERING INFORMATION - VDD = 3.3V Commercial Range 0°C to 70°C Frequency 166 MHz 166 MHz 166 MHz 166 MHz 143 MHz 143 MHz 143 MHz 143 MHz Speed ns 6 7 Order Part No. IS42S32400B-6T IS42S32400B-6TL IS42S32400B-6B IS42S32400B-6BL IS42S32400B-7T IS42S32400B-7TL IS42S32400B-7B IS42S32400B-7BL ORDERING INFORMATION - VDD = 3.3V Industrial Range -40°C to 85°C Frequency 166 MHz 166 MHz 166 MHz 143 MHz 143 MHz 143 MHz 143 MHz Speed ns 6 7 Order Part No. IS42S32400B-6TI IS42S32400B-6TLI IS42S32400B-6BLI IS42S32400B-7TI IS42S32400B-7TLI IS42S32400B-7BI IS42S32400B-7BLI Package 86-Pin TSOPII 86-Pin TSOPII, Lead-free 90-Ball FBGA 90-Ball FBGA, Lead-free 86-Pin TSOPII 86-Pin TSOPII, Lead-free 90-Ball FBGA 90-Ball FBGA, Lead-free Package 86-Pin TSOPII 86-Pin TSOPII, Lead-free 90-Ball FBGA, Lead-free 86-Pin TSOPII 86-Pin TSOPII, Lead-free 90-Ball FBGA 90-Ball FBGA, Lead-free Integrated Silicon Solution, Inc. 1-800-379-4774 03/03/09 NOTE : Controlling dimension mm Dimension D and E1 do not include mold protrusion Dimension b does not include dambar protrusion/intrusion. Formed leads shall be planar with respect to one another within 0.1mm at the seating plane after final test. 09/26/2006 NOTE : CONTROLLING DIMENSION MM Reference document JEDEC MO-207 08/14/2008

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IS42S32400B
4Meg x 32 128-MBIT SYNCHRONOUS DRAM

PRELIMINARY INFORMATION MARCH 2009
• Clock frequency 166, 143, 125, 100 MHz
• Fully synchronous all signals referenced to a positive clock edge
• Internal bank for hiding row access/precharge
• Power supply

IS42S32400B

VDD VDDQ 3.3V 3.3V
• LVTTL interface
• Programmable burst length 1, 2, 4, 8, full page
• Programmable burst sequence Sequential/Interleave
• Auto Refresh CBR
• Self Refresh with programmable refresh periods
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency 2, 3 clocks
• Burst read/write and burst read/single write operations capability
• Burst termination by burst stop and precharge command
• Available in Industrial Temperature
• Available in 86-pin TSOP-II and 90-ball FBGA
• Available in Lead-free

OVERVIEW

ISSI's 128Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks.

KEY TIMING PARAMETERS

Parameter

Unit

Clk Cycle Time CAS Latency = 3 CAS Latency = 2

Clk Frequency CAS Latency = 3 CAS Latency = 2
166 143
125 100

Access Time from Clock

CAS Latency = 3

CAS Latency = 2

Copyright 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. 1-800-379-4774
03/03/09

IS42S32400B

DEVICE OVERVIEW

The 128Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V VDD and 3.3V VDDQ memory systems containing 134,217,728 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 33,554,432-bit bank is organized as 4,096 rows by 256 columns by 32 bits.

The 128Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible.
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in BURST DEFINITION table.

BURST DEFINITION

Burst Length

Full Page y

Starting Column

Address

A1 A0

A2 A1 A0
n = A0-A7
location 0-y

Order of Accesses Within a Burst

Type = Sequential

Type = Interleaved
0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2
0-1-2-3 1-0-3-2-3-0-1 3-2-1-0
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn + 1, Cn + 2 Cn + 3, Cn +
0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not Supported

Integrated Silicon Solution, Inc. 1-800-379-4774

IS42S32400B

CAS Latency

The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier n + m - 1 , and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in CAS Latency diagrams. The Allowable Operating Frequency table indicates the operating frequencies at which each CAS latency setting can be used.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Operating Mode

The normal operating mode is selected by setting M7 and M8 to zero the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts.

Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location nonburst accesses.

CAS Latency

Allowable Operating Frequency MHz

Speed

CAS Latency = 2

CAS Latency = 3

CAS LATENCY

COMMAND DQ

READ

DOUT

CAS Latency - 2

T0 CLK

COMMAND READ

NOP tAC
ORDERING INFORMATION - VDD = 3.3V Commercial Range 0°C to 70°C

Frequency 166 MHz 166 MHz 166 MHz 166 MHz 143 MHz 143 MHz 143 MHz 143 MHz

Speed ns 6 7

Order Part No. IS42S32400B-6T IS42S32400B-6TL IS42S32400B-6B IS42S32400B-6BL IS42S32400B-7T IS42S32400B-7TL IS42S32400B-7B IS42S32400B-7BL
ORDERING INFORMATION - VDD = 3.3V Industrial Range -40°C to 85°C

Frequency 166 MHz 166 MHz 166 MHz 143 MHz 143 MHz 143 MHz 143 MHz

Speed ns 6 7

Order Part No. IS42S32400B-6TI IS42S32400B-6TLI IS42S32400B-6BLI IS42S32400B-7TI IS42S32400B-7TLI IS42S32400B-7BI IS42S32400B-7BLI

Package 86-Pin TSOPII 86-Pin TSOPII, Lead-free 90-Ball FBGA 90-Ball FBGA, Lead-free 86-Pin TSOPII 86-Pin TSOPII, Lead-free 90-Ball FBGA 90-Ball FBGA, Lead-free

Package 86-Pin TSOPII 86-Pin TSOPII, Lead-free 90-Ball FBGA, Lead-free 86-Pin TSOPII 86-Pin TSOPII, Lead-free 90-Ball FBGA 90-Ball FBGA, Lead-free

Integrated Silicon Solution, Inc. 1-800-379-4774
03/03/09

NOTE :

Controlling dimension mm Dimension D and E1 do not include mold protrusion Dimension b does not include dambar protrusion/intrusion. Formed leads shall be planar with respect to one another within 0.1mm
at the seating plane after final test.
09/26/2006

NOTE :

CONTROLLING DIMENSION MM Reference document JEDEC MO-207
08/14/2008

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IS42S32400B-7TI-TR Datasheet file may be downloaded here without warranties.

Datasheet ID: IS42S32400B-7TI-TR 639293