MPC9865VMR2

MPC9865VMR2 Datasheet

MPC9865

Part	Datasheet
MPC9865VMR2	MPC9865VMR2 (pdf)

Related Parts	Information
MPC9865VM	MPC9865VM

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Freescale Semiconductor Technical Data MPC9865 RDeAv T2,AMSayH/2E00E6T CloAckdvGaennceeraItnofrofromr PaotiwonerQUICC III Clock Generator for PowerQUICC III MPC9865 The MPC9865 is a PLL based clock generator specifically designed for Freescale Microprocessor and Microcontroller applications including the PowerPC and PowerQUICC. This device generates a microprocessor input clock. The microprocessor clock is selectable in output frequency to any of the commonly used microprocessor input and bus frequencies. The device offers eight low skew clock outputs in two banks, each configurable to support different clock frequencies. The extended temperature range of the MPC9865 supports telecommunication and networking requirements. MICROPROCESSOR CLOCK GENERATOR • 8 LVCMOS outputs for processor and other circuitry • Crystal oscillator or external reference input • 25 or 33 MHz Input reference frequency • Selectable output frequencies include = 200, 166, 133,125, 111, 100, 83, 66, 50, 33, or 16 MHz • Buffered reference clock output 2 copies • Low cycle-to-cycle and period jitter • 100-lead PBGA package • 100-lead Pb-free package available • V supply with V or V LVCMOS output supplies • Supports computing, networking, telecommunications applications • Ambient temperature range to +85°C SCALE 2 1 VF SUFFIX VM SUFFIX PB-FREE 100 MAPBGA PACKAGE CASE 1462-01 Functional Description The MPC9865 uses either a 25 or 33 MHz reference frequency to generate 8 LVCMOS output clocks, of which, the frequency is selectable from 16 MHz to 200 MHz. The reference is applied to the input of a PLL and multiplied to 2 GHz. Output dividers, divide this frequency by 10, 12, 15, 16, 18, 20, 24, 30, 40, 60, or 120 to produce output frequencies of 200, 166, 133, 125, 111, 100, 83, 66, 50, 33, or 16 MHz. The single-ended LVCMOS outputs provide 8 low skew outputs for use in driving a microprocessor or microcontroller clock input as well as other system components. The input reference, either crystal or external input is also buffered to a separate dual outputs that my be used as the clock source for a Ethernet PHY if desired. The reference clock may be provided by either an external clock input of 25 or 33 MHz. An internal oscillator requiring a 25 MHz crystal for frequency control may also be used. The external clock source my be applied to either of two clock inputs and selected via the CLK_SEL control input. Both single ended LVCMOS and differential LVPECL inputs are available. The crystal oscillator or external clock input is selected via the input pin of XTAL_SEL. Other than the crystal, no external components are required for crystal oscillator operation. The REF_33 MHz configuration pin is used to select between a 33 and 25 MHz input frequency. The MPC9865 is packaged in a 100 lead MAPBGA package to optimize both performance and board density. IDT CIncII.I, All rights reserved. Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc MPC9865 MPC9865 Clock Generator for PowerQUICC III PCLK 1 ÷N PCLK CLK_SEL XTAL_IN OSC XTAL_OUT 2000 MHz XTAL_SEL ÷N PLL_BYPASS REF_33 MHz CLK_A[0:5] CLK_B[0:5] REF_OUT1_E Figure MPC9865 Logic Diagram NETCOM QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 REF_OUT0 REF_OUT1 IDT CloMckPGCe9n8e6r5ator for PowerQUICC III Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc MPC9865 Advanced Clock Drivers Devices Freescale Semiconductor MPC9865 Clock Generator for PowerQUICC III NETCOM Table Pin Configurations PowerPC bit ordering bit 0 = msb, bit 5 = lsb . PowerPC bit ordering bit 0 = msb, bit 5 = lsb . Supply VDD Active/State VDDOA High High Low High Table Function Table Control Default CLK_SEL XTAL_SEL CLKx PLL_BYPASS Normal REF_OUT1_E Disables REF_OUT1 REF_33 MHz Selects 25 MHz Reference Reset CLK_A and CLK_B control output frequencies. See Table 3 for specific device configuration. 1 PCLK XTAL Bypass Enables REF_OUT1 Selects 33 MHz Reference Normal IDT Clock Generator for PowerQUICC III been acquired by Integrated Device Technology, Inc Freescale Semiconductor MPC9865MPC9865 3 MPC9865 Clock Generator for PowerQUICC III NETCOM Table Output Configurations Banks A & B CLK_x[0:5] 1 111100 101000 011110 010100 010000 001111 001100 001010 001001 001000 000111 000110 000101 000100 CLK_x[0] msb 1 0 CLK_x[1] 1 0 1 0 CLK_x[2] 1 0 1 0 PowerPC bit ordering bit 0 = msb, bit 5 = lsb . Minimum value for N. CLK_x[3] 1 0 1 0 1 0 1 CLK_x[4] 1 0 1 0 1 0 1 0 1 0 CLK_x[5] lsb 1 0 1 0 1 0 1 0 1 0 Frequency MHz IDT CloMckPGCe9n8e6r5ator for PowerQUICC III Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc MPC9865 Advanced Clock Drivers Devices Freescale Semiconductor MPC9865 Clock Generator for PowerQUICC III NETCOM OPERATION INFORMATION Output Frequency Configuration The MPC9865 was designed to provide the commonly used frequencies in PowerQUICC, PowerPC and other microprocessor systems. Table 3 lists the configuration values that will generate those common frequencies. The MPC9865 can generate numerous other frequencies that may be useful in specific applications. The output frequency fout of either Bank A or Bank B may be calculated by the following equation. fout = 2000 / N where fout is in MHz and N = 2 * CLK_x[0:5] This calculation is valid for all values of N from 8 to Note that N = 15 is a modified case of the configuration inputs CLK_x[0:5]. To achieve N = 15 CLK_x[0:5] is configured to 00111 or Crystal Input Operation TBD Power-Up and MR Operation Figure 2 defines the release time and the minimum pulse length for MR pin. The MR release time is based upon the power supply being stable and within VDD specifications. See Table 9 for actual parameter values. The MPC9865 may be configured after release of reset and the outputs will be stable for use after lock indication is obtained. MR treset_rel treset_pulse Figure MR Operation Power Supply Bypassing The MPC9865 is a mixed analog/digital product. The architecture of the MPC9865 supports low noise signal operation at high frequencies. In order to maintain its superior signal quality, all VDD pins should be bypassed by high-frequency ceramic capacitors connected to GND. If the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth. 22 uF MPC9865 15 Ω VDDA Power Consumption Calculation For unloaded outputs the power consumption of the MPC9855 can be calculated as follows. P = VDD * IDDBASE + nA * VDDOA ** 2 * CPD * fA + nB * VDDOB ** 2 * CPD * fB where VDD = core supply voltage IDDBASE = base supply current nA = number of A bank outputs = 4 nB = number of B bank outputs = 4 VDDOA = voltage supply on bank A outputs VDDOB = voltage supply on bank B outputs CPD = power dissipation capacitance fA = frequency of bank A outputs fB = frequency of bank B outputs Figure VCC Power Supply Bypass IDT Clock Generator for PowerQUICC III been acquired by Integrated Device Technology, Inc

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Freescale Semiconductor Technical Data

MPC9865

RDeAv T2,AMSayH/2E00E6T

CloAckdvGaennceeraItnofrofromr PaotiwonerQUICC III Clock Generator for PowerQUICC III

MPC9865

The MPC9865 is a PLL based clock generator specifically designed for Freescale Microprocessor and Microcontroller applications including the PowerPC and PowerQUICC. This device generates a microprocessor input clock. The microprocessor clock is selectable in output frequency to any of the commonly used microprocessor input and bus frequencies. The device offers eight low skew clock outputs in two banks, each configurable to support different clock frequencies. The extended temperature range of the MPC9865 supports telecommunication and networking requirements.

MICROPROCESSOR CLOCK GENERATOR
• 8 LVCMOS outputs for processor and other circuitry
• Crystal oscillator or external reference input
• 25 or 33 MHz Input reference frequency
• Selectable output frequencies include = 200, 166, 133,125, 111, 100, 83, 66,
50, 33, or 16 MHz
• Buffered reference clock output 2 copies
• Low cycle-to-cycle and period jitter
• 100-lead PBGA package
• 100-lead Pb-free package available
• V supply with V or V LVCMOS output supplies
• Supports computing, networking, telecommunications applications
• Ambient temperature range to +85°C

SCALE 2 1

VF SUFFIX VM SUFFIX PB-FREE 100 MAPBGA PACKAGE

CASE 1462-01

Functional Description

The MPC9865 uses either a 25 or 33 MHz reference frequency to generate 8 LVCMOS output clocks, of which, the frequency is selectable from 16 MHz to 200 MHz. The reference is applied to the input of a PLL and multiplied to 2 GHz. Output dividers, divide this frequency by 10, 12, 15, 16, 18, 20, 24, 30, 40, 60, or 120 to produce output frequencies of 200, 166, 133, 125, 111, 100, 83, 66, 50, 33, or 16 MHz. The single-ended LVCMOS outputs provide 8 low skew outputs for use in driving a microprocessor or microcontroller clock input as well as other system components. The input reference, either crystal or external input is also buffered to a separate dual outputs that my be used as the clock source for a Ethernet PHY if desired.

The reference clock may be provided by either an external clock input of 25 or 33 MHz. An internal oscillator requiring a 25 MHz crystal for frequency control may also be used. The external clock source my be applied to either of two clock inputs and selected via the CLK_SEL control input. Both single ended LVCMOS and differential LVPECL inputs are available. The crystal oscillator or external clock input is selected via the input pin of XTAL_SEL. Other than the crystal, no external components are required for crystal oscillator operation. The REF_33 MHz configuration pin is used to select between a 33 and 25 MHz input frequency.

The MPC9865 is packaged in a 100 lead MAPBGA package to optimize both performance and board density.

IDT CIncII.I, All rights reserved. Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

MPC9865

MPC9865 Clock Generator for PowerQUICC III

PCLK
1 ÷N

PCLK

CLK_SEL

XTAL_IN OSC

XTAL_OUT
2000 MHz

XTAL_SEL ÷N

PLL_BYPASS REF_33 MHz

CLK_A[0:5] CLK_B[0:5]

REF_OUT1_E

Figure MPC9865 Logic Diagram

NETCOM

QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3

REF_OUT0 REF_OUT1

IDT CloMckPGCe9n8e6r5ator for PowerQUICC III

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

MPC9865 Advanced Clock Drivers Devices

Freescale Semiconductor

MPC9865 Clock Generator for PowerQUICC III

NETCOM

Table Pin Configurations
PowerPC bit ordering bit 0 = msb, bit 5 = lsb . PowerPC bit ordering bit 0 = msb, bit 5 = lsb .

Supply VDD

Active/State

VDDOA

High

High Low High

Table Function Table

Control

Default

CLK_SEL

XTAL_SEL

CLKx

PLL_BYPASS

Normal

REF_OUT1_E

Disables REF_OUT1

REF_33 MHz

Selects 25 MHz Reference

Reset

CLK_A and CLK_B control output frequencies. See Table 3 for specific device configuration.
1 PCLK XTAL Bypass Enables REF_OUT1 Selects 33 MHz Reference Normal

IDT Clock Generator for PowerQUICC III
been acquired by Integrated Device Technology, Inc

Freescale Semiconductor

MPC9865MPC9865 3

MPC9865 Clock Generator for PowerQUICC III

NETCOM

Table Output Configurations Banks A & B

CLK_x[0:5] 1
111100 101000 011110 010100 010000 001111 001100 001010 001001 001000 000111 000110 000101 000100

CLK_x[0] msb 1 0

CLK_x[1]
1 0 1 0

CLK_x[2]
1 0 1 0
PowerPC bit ordering bit 0 = msb, bit 5 = lsb . Minimum value for N.

CLK_x[3]
1 0 1 0 1 0 1

CLK_x[4]
1 0 1 0 1 0 1 0 1 0

CLK_x[5] lsb 1 0 1 0 1 0 1 0 1 0

Frequency MHz

IDT CloMckPGCe9n8e6r5ator for PowerQUICC III

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

MPC9865 Advanced Clock Drivers Devices

Freescale Semiconductor

MPC9865 Clock Generator for PowerQUICC III

NETCOM

OPERATION INFORMATION

Output Frequency Configuration

The MPC9865 was designed to provide the commonly used frequencies in PowerQUICC, PowerPC and other microprocessor systems. Table 3 lists the configuration values that will generate those common frequencies. The MPC9865 can generate numerous other frequencies that may be useful in specific applications. The output frequency fout of either Bank A or Bank B may be calculated by the following equation.
fout = 2000 / N
where fout is in MHz and N = 2 * CLK_x[0:5] This calculation is valid for all values of N from 8 to

Note that N = 15 is a modified case of the configuration inputs

CLK_x[0:5]. To achieve N = 15 CLK_x[0:5] is configured to 00111 or

Crystal Input Operation TBD

Power-Up and MR Operation Figure 2 defines the release time and the minimum pulse
length for MR pin. The MR release time is based upon the power supply being stable and within VDD specifications. See Table 9 for actual parameter values. The MPC9865 may be configured after release of reset and the outputs will be stable for use after lock indication is obtained.

MR treset_rel
treset_pulse

Figure MR Operation

Power Supply Bypassing

The MPC9865 is a mixed analog/digital product. The architecture of the MPC9865 supports low noise signal operation at high frequencies. In order to maintain its superior signal quality, all VDD pins should be bypassed by high-frequency ceramic capacitors connected to GND. If the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth.
22 uF

MPC9865
15 Ω

VDDA

Power Consumption Calculation

For unloaded outputs the power consumption of the

MPC9855 can be calculated as follows.

P = VDD * IDDBASE + nA * VDDOA ** 2 * CPD * fA
+ nB * VDDOB ** 2 * CPD * fB where

VDD = core supply voltage IDDBASE = base supply current nA = number of A bank outputs = 4 nB = number of B bank outputs = 4 VDDOA = voltage supply on bank A outputs VDDOB = voltage supply on bank B outputs CPD = power dissipation capacitance fA = frequency of bank A outputs fB = frequency of bank B outputs

Figure VCC Power Supply Bypass

IDT Clock Generator for PowerQUICC III
been acquired by Integrated Device Technology, Inc

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Datasheet ID: MPC9865VMR2 637499