MPC92432AE

MPC92432AE Datasheet

MPC92432

Part	Datasheet
MPC92432AE	MPC92432AE (pdf)

Related Parts	Information
MPC92432AER2	MPC92432AER2

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Freescale Semiconductor Technical Data uLVtpPuEtCLLVPECL Clock Synthesizer DATMAPCS9H2E43E2T MPC92432 MPC92432 The MPC92432 is a V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking, and computing applications. With output frequencies from MHz to 1360 MHz and the support of two differential PECL output signals, the device meets the needs of the most demanding clock applications. • MHz to 1360 MHz synthesized clock output signal • Two differential, LVPECL-compatible high-frequency outputs • Output frequency programmable through 2-wire I2C bus or parallel interface • On-chip crystal oscillator for reference frequency generation • Alternative LVCMOS compatible reference clock input • Synchronous clock stop functionality for both outputs • LOCK indicator output LVCMOS • LVCMOS compatible control inputs • Fully integrated PLL • 3.3-V power supply • 48-lead LQFP • 48-lead Pb-free package available • SiGe Technology • Ambient temperature range to +85°C Applications • Programmable clock source for server, computing, and telecommunication systems • Frequency margining • Oscillator replacement 1360 MHz LOW VOLTAGE CLOCK SYNTHESIZER FA SUFFIX 1 48-LEAD LQFP PACKAGE CASE 932-03 AE SUFFIX 2 48-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 932-03 Functional Description The MPC92432 is a programmable high-frequency clock source clock synthesizer . The internal PLL generates a high- frequency output signal based on a low-frequency reference signal. The frequency of the output signal is programmable and can be changed on the fly for frequency margining purpose. The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. Alternatively, a LVCMOS compatible clock signal can be used as a PLL reference signal. The frequency of the internal crystal oscillator is divided by a selectable divider and then multiplied by the PLL. The VCO within the PLL operates over a range of 1360 to 2720 MHz. Its output is scaled by a divider that is configured by either the I2C or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL predivider P, the feedback-divider M, and the PLL post-divider N determine the output frequency. The feedback path of the PLL is internal. The PLL post-divider N is configured through either the I2C or the parallel interfaces, and can provide one of six division ratios 2, 4, 8, 16, 32, This divider extends the performance of the part while providing a 50% duty cycle. The high-frequency outputs, QA and QB, are differential and are capable of driving a pair of transmission lines terminated 50 to VCC V. The second high-frequency output, QB, can be configured to run at either 1x or 1/2x of the clock frequency or the first output QA . The positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise induced jitter. The configuration logic has two sections I2C and parallel. The parallel interface uses the values at the M[9:0], NA[2:0], NB, and P parallel inputs to configure the internal PLL dividers. The parallel programming interface has priority over the serial I2C interface. The serial interface is I2C compatible and provides read and write access to the internal PLL configuration registers. The lock state of the PLL is indicated by the LVCMOS-compatible LOCK output. FA suffix leaded terminations. AE suffix lead-free, EPP and RoHS-compliant. IDT 1360 MHz Dual Output LVPECL Clock Synthesizer h2a0s05b.eAenll raicgqhutsirreedsbeyrvIendte. grated Device Technology, Inc MPC92432 MPC92432 1360 MHz Dual Output LVPECL Clock Synthesizer NETCOM REF_CLK XTAL1 XTAL2 REF_SEL TEST_EN SDA SCL ADR[1:0] PLOAD M[9:0] NA[2:0] NB CLK_STOPx BYPASS MR XTAL ÷P fREF PLL Configuration Registers I2C Control fVCO

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Freescale Semiconductor Technical Data
uLVtpPuEtCLLVPECL Clock Synthesizer

DATMAPCS9H2E43E2T

MPC92432

MPC92432

The MPC92432 is a V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking, and computing applications. With output frequencies from MHz to 1360 MHz and the support of two differential PECL output signals, the device meets the needs of the most demanding clock applications.
• MHz to 1360 MHz synthesized clock output signal
• Two differential, LVPECL-compatible high-frequency outputs
• Output frequency programmable through 2-wire I2C bus or parallel interface
• On-chip crystal oscillator for reference frequency generation
• Alternative LVCMOS compatible reference clock input
• Synchronous clock stop functionality for both outputs
• LOCK indicator output LVCMOS
• LVCMOS compatible control inputs
• Fully integrated PLL
• 3.3-V power supply
• 48-lead LQFP
• 48-lead Pb-free package available
• SiGe Technology
• Ambient temperature range to +85°C

Applications
• Programmable clock source for server, computing, and telecommunication systems
• Frequency margining
• Oscillator replacement
1360 MHz LOW VOLTAGE CLOCK SYNTHESIZER

FA SUFFIX 1 48-LEAD LQFP PACKAGE

CASE 932-03

AE SUFFIX 2 48-LEAD LQFP PACKAGE

Pb-FREE PACKAGE CASE 932-03

Functional Description

The MPC92432 is a programmable high-frequency clock source clock synthesizer . The internal PLL generates a high-
frequency output signal based on a low-frequency reference signal. The frequency of the output signal is programmable and can
be changed on the fly for frequency margining purpose.

The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. Alternatively, a LVCMOS
compatible clock signal can be used as a PLL reference signal. The frequency of the internal crystal oscillator is divided by a
selectable divider and then multiplied by the PLL. The VCO within the PLL operates over a range of 1360 to 2720 MHz. Its output is scaled by a divider that is configured by either the I2C or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL predivider P, the feedback-divider M, and the PLL post-divider N determine the output frequency. The feedback path of the PLL is
internal. The PLL post-divider N is configured through either the I2C or the parallel interfaces, and can provide one of six division ratios
2, 4, 8, 16, 32, This divider extends the performance of the part while providing a 50% duty cycle. The high-frequency outputs, QA and QB, are differential and are capable of driving a pair of transmission lines terminated 50 to VCC V. The second high-frequency output, QB, can be configured to run at either 1x or 1/2x of the clock frequency or the first output QA . The positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise
induced jitter. The configuration logic has two sections I2C and parallel. The parallel interface uses the values at the M[9:0], NA[2:0], NB,
and P parallel inputs to configure the internal PLL dividers. The parallel programming interface has priority over the serial I2C interface. The serial interface is I2C compatible and provides read and write access to the internal PLL configuration registers.

The lock state of the PLL is indicated by the LVCMOS-compatible LOCK output.

FA suffix leaded terminations. AE suffix lead-free, EPP and RoHS-compliant.

IDT 1360 MHz Dual Output LVPECL Clock Synthesizer h2a0s05b.eAenll raicgqhutsirreedsbeyrvIendte. grated Device Technology, Inc

MPC92432

MPC92432 1360 MHz Dual Output LVPECL Clock Synthesizer

NETCOM

REF_CLK XTAL1 XTAL2

REF_SEL

TEST_EN

SDA SCL ADR[1:0] PLOAD M[9:0] NA[2:0] NB

CLK_STOPx BYPASS MR

XTAL
÷P fREF

PLL Configuration

Registers

I2C Control
fVCO

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Datasheet ID: MPC92432AE 637494