MPC905EF

MPC905EF Datasheet

MPC905

Part	Datasheet
MPC905EF	MPC905EF (pdf)

Related Parts	Information
MPC905EFR2	MPC905EFR2
MPC905DR2	MPC905DR2

PDF Datasheet Preview
1:6 PCI Clock Generator/Fanout Buffer Product Discontinuance Notice Last Time Buy Expires on 12/7/2013 MPC905 DATASHEET 1:6 PCI Clock Generator/ Fanout Buffer The MPC905 is a six output clock generation device targeted to provide the clocks required in a V or V PCI environment. The device operates from a V supply and can interface to either a TTL input or an external crystal. The inputs to the device can be driven with V when the VCC is at V. The outputs of the MPC905 meet all of the specifications of the PCI standard. • Six Low Skew Outputs • Synchronous Output Enables for Power Management • Low Voltage Operation • XTAL Oscillator Interface • 16-Lead SOIC Package • V Tolerant Enable Inputs • Replacement part ICS83905 1:6 PCI CLOCK GENERATOR/ FANOUT BUFFER SCALE 2:1 Functional Description The MPC905 device is targeted for PCI bus or processor bus environments with up to 12 clock loads. Each of the six outputs on the MPC905 can drive two series terminated transmission lines. This capability effectively makes the D SUFFIX EF SUFFIX PB-FREE PACKAGE PLASTIC SOIC PACKAGE CASE 751B-05 MPC905 a 1:12 fanout buffer. The MPC905 offers two synchronous enable inputs to allow users flexibility in developing power management features for their designs. Both enable signals are active HIGH inputs. A logic ‘0’ on the ENABLE1 will pull outputs 0 to 4 into the logic ‘0’ state. A logic ‘1’ on the ENABLE1 input will result in outputs 0 to 4 to be toggling. A logic ‘0’ on ENABLE2 will cause output BLK5 to a logic ‘0’ state, whereas a logic ‘1’ on ENABLE2 will cause output BLK5 to toggle. The oscillator remains on. The ENABLE2 input can be used to disable any high power device for system power savings during periods of inactivity. Both enable inputs are synchronized internal to the chip so that the output disabling will happen only when the outputs are already LOW. This feature guarantees no runt pulses will be generated during enabling and disabling. 2012 Integrated Device Technology, Inc. MPC905 Data Sheet 1:6 PCI CLOCK GENERATOR/FANOUT BUFFR VDD 3 GND 3 XTAL_IN XTAL_OUT ENABLE1 ENABLE2 SYNCHRONIZE Figure Block Diagram BCLK0 BCLK1 BCLK2 BCLK3 BCLK4 BCLK5 XTAL_OUT 1 ENABLE2 2 GND1 3 BCLKO 4 VDD1 5 BCLK1 6 GND2 7 BCLK2 8 16 XTAL_IN 15 ENABLE1 14 BCLK5 13 VDD3 12 BCLK4 11 GND3 10 BCLK3 9 VDD2 Figure Pinout 16-Lead Plastic Package Top View Table Pin Configurations Pin XTAL_IN, XTAL_OUT ENABLE1, ENABLE2 VDD GND I/O Input Output Type Analog LVCMOS Supply Function Crystal Oscillator Terminals Output Enable Clock Outputs Positive Power Supply Negative Power Supply Table Function Table

PDF Datasheet Preview

1:6 PCI Clock Generator/Fanout Buffer

Product Discontinuance Notice Last Time Buy Expires on 12/7/2013

MPC905

DATASHEET
1:6 PCI Clock Generator/ Fanout Buffer

The MPC905 is a six output clock generation device targeted to provide the clocks required in a V or V PCI environment. The device operates from a V supply and can interface to either a TTL input or an external crystal. The inputs to the device can be driven with V when the VCC is at V. The outputs of the MPC905 meet all of the specifications of the PCI standard.
• Six Low Skew Outputs
• Synchronous Output Enables for Power Management
• Low Voltage Operation
• XTAL Oscillator Interface
• 16-Lead SOIC Package
• V Tolerant Enable Inputs
• Replacement part ICS83905
1:6 PCI CLOCK GENERATOR/

FANOUT BUFFER

SCALE 2:1

Functional Description

The MPC905 device is targeted for PCI bus or processor bus environments with up to 12 clock loads. Each of the six outputs on the MPC905 can drive two series terminated transmission lines. This capability effectively makes the

D SUFFIX EF SUFFIX PB-FREE PACKAGE

PLASTIC SOIC PACKAGE CASE 751B-05

MPC905 a 1:12 fanout buffer.

The MPC905 offers two synchronous enable inputs to allow users flexibility in
developing power management features for their designs. Both enable signals are active HIGH inputs. A logic ‘0’ on the

ENABLE1 will pull outputs 0 to 4 into the logic ‘0’ state. A logic ‘1’ on the ENABLE1 input will result in outputs 0 to 4 to be toggling.

A logic ‘0’ on ENABLE2 will cause output BLK5 to a logic ‘0’ state, whereas a logic ‘1’ on ENABLE2 will cause output BLK5 to
toggle. The oscillator remains on.

The ENABLE2 input can be used to disable any high power device for system power savings during periods of inactivity. Both
enable inputs are synchronized internal to the chip so that the output disabling will happen only when the outputs are already

LOW. This feature guarantees no runt pulses will be generated during enabling and disabling.
2012 Integrated Device Technology, Inc.

MPC905 Data Sheet
1:6 PCI CLOCK GENERATOR/FANOUT BUFFR

VDD 3 GND 3

XTAL_IN

XTAL_OUT ENABLE1 ENABLE2

SYNCHRONIZE

Figure Block Diagram

BCLK0 BCLK1 BCLK2 BCLK3 BCLK4 BCLK5

XTAL_OUT 1 ENABLE2 2 GND1 3 BCLKO 4 VDD1 5 BCLK1 6 GND2 7 BCLK2 8
16 XTAL_IN 15 ENABLE1 14 BCLK5 13 VDD3 12 BCLK4 11 GND3 10 BCLK3 9 VDD2

Figure Pinout 16-Lead Plastic Package Top View

Table Pin Configurations

Pin XTAL_IN, XTAL_OUT ENABLE1, ENABLE2 VDD GND

I/O Input Output

Type Analog LVCMOS Supply

Function Crystal Oscillator Terminals Output Enable Clock Outputs Positive Power Supply Negative Power Supply

Table Function Table

More datasheets: 1N4942-AP | 1N4948-AP | 1N4947-AP | 1N4944-AP | 1N4942-TP | 1N4944-TP | 1N4946-TP | 1N4948-TP | 1N4946-AP | 1N4947-TP

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Datasheet ID: MPC905EF 637492