M2020-11-625.0000T

M2020-11-625.0000T Datasheet

M2020/21

Part	Datasheet
M2020-11-625.0000T	M2020-11-625.0000T (pdf)

Related Parts	Information
M2020-11-622.0800	M2020-11-622.0800
M2021-11-622.0800T	M2021-11-622.0800T
M2021-11-622.0800	M2021-11-622.0800
M2020-11-622.0800T	M2020-11-622.0800T
M2020-13-622.0800	M2020-13-622.0800
M2021-13-622.0800	M2021-13-622.0800
M2020-11-669.3266	M2020-11-669.3266
M2021-13-622.0800T	M2021-13-622.0800T
M2020-13I622.0800	M2020-13I622.0800
M2020-11-669.3266T	M2020-11-669.3266T
M2020-13I622.0800T	M2020-13I622.0800T
M2020-11-625.0000	M2020-11-625.0000

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Integrated Circuit Systems, Inc. M2020/21 VCSO BASED CLOCK PLL The M2020/21 is a VCSO Voltage Controlled SAW Oscillator based clock jitter attenuator PLL designed for clock jitter attenuation and frequency translation. The device is ideal for generating the transmit reference clock for optical network systems supporting GB data rates. It can serve to jitter attenuate a stratum reference clock or a recovered clock in loop timing mode. The M2020/21 module includes a proprietary SAW surface acoustic wave delay line as part of the VCSO. This results in a high frequency, high-Q, low phase noise oscillator that assures low intrinsic output jitter. Integrated SAW surface acoustic wave delay line low phase jitter of < 0.5ps rms, typical 12kHz to 20MHz or 50kHz to 80MHz Output frequencies of 15 to 700 MHz * LVPECL clock output CML and LVDS options available Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL Loss of Lock LOL output pin Narrow Bandwidth control input NBW pin Hitless Switching HS options with or without Phase Build-out PBO available for SONET GR-253 / SDH G.813 MTIE and TDEV compliance during reference clock reselection Industrial temperature grade available Single 3.3V power supply Small 9 x 9 mm SMT surface mount package PIN ASSIGNMENT 9 x 9 mm SMT nDIF_REF1 DIF_REF1 REF_SEL nDIF_REF0 DIF_REF0 P_SEL2 FIN_SEL1 FIN_SEL0 MR_SEL0 MR_SEL1 LOL NBW VCC DNC M2020 M2021 Top View P_SEL0 P_SEL1 nFOUT0 FOUT0 GND nFOUT1 FOUT1 VCC GND nOP_IN OP_OUT nOP_OUT OP_IN Figure 1 Pin Assignment Example I/O Clock Frequency Combinations Using M2020-11-622.0800 or M2021-11-622.0800 Input Reference Clock MHz PLL Ratio Pin Selectable Output Clock MHz M2020 M2021 M2020 M2021 32 or 16 8 4 1 An internal high "Q" SAW delay line provides low jitter signal performance and establishes the output frequency of the VCSO Voltage Controlled SAW Oscillator . In a given M2020/21 device, the VCSO center frequency is fixed. A common center frequency is 622.08MHz, for SONET for SDH optical network applications. The VCSO center frequency is specified at time of order see “Ordering Information” on pg. The VCSO has a guaranteed tuning range of ±120 ppm commercial temperature grade . Pin selectable dividers are used within the PLL and for the output clock. This enables tailoring of device functionality and performance. The Mfin divider controls the overall PLL multiplication ratio and thus determines the input reference clock see Table 3, on pg. The M and R dividers control the phase detector frequency see Table The P divider scales the VCSO output enabling lower output frequency selections Table The M2020/21 includes a Loss of Lock LOL indicator, which provides status information to system management software. A Narrow Bandwidth NBW control pin is provided as an additional mechanism for adjusting PLL loop bandwidth without affecting the phase detector frequency. Options are available for Hitless Switching HS with or without Phase Build-out PBO . They provide SONET/SDH MTIE and TDEV compliance during a reference clock reselection. Allowance for a single-ended input has been facilitated by a unique input resistor bias scheme, which is described next and shown in Figure Input Reference Clocks Two clock reference inputs and a selection mux are provided. Either reference clock input can accept a differential clock signal such as LVPECL or LVDS or a single-ended clock input LVCMOS or LVTTL on the non-inverting input . A single-ended reference clock on the unselected reference input can cause an increase in output clock jitter. For this reason, differential reference inputs are preferred interference from a differential input on the non-selected input is minimal. M2020/21 VCSO BASED CLOCK PLL Configuration of a single-ended input has been facilitated by biasing nDIF_REF0 and nDEF_REF1 to Vcc/2, with to Vcc and to ground. The input clock structure, and how it is used with either LVCMOS/LVTTL inputs or a DC- coupled LVPECL clock, is shown in Figure DIF_REF0 LVCMOS/ LVTTL nDIF_REF0 DIF_REF1 LVPECL nDIF_REF1 REF_SEL Figure 4 Input Reference Clocks M2020/21 Differential Inputs Differential LVPECL inputs are connected to both reference input pins in the usual manner. The external load termination resistors shown in Figure 4 the and resistors is ideally suited for both AC and DC coupled LVPECL reference clock lines. These provide the load termination and the VTT bias voltage. Single-ended Inputs Single-ended inputs LVCMOS or LVTTL are connected to the non-inverting reference input pin DIF_REF0 or DIF_REF1 . The inverting reference input pin nDIF_REF0 or nDIF_REF1 must be left unconnected. In single-ended operation, when the unused inverting input pin nDIF_REF0 or nDEF_REF1 is left floating not connected , the input will self-bias at VCC/2. PLL Operation The M2020/21 is a complete clock PLL. It uses a phase detector and configurable dividers to synchronize the output of the VCSO with the selected reference clock. The PLL will work correctly, meaning it will phase-lock the VCSO output to the input reference clock, when the internal phase detector inputs are able to run at the same frequency. This means the PLL dividers must be set appropriately and a suitable reference frequency must be chosen for the intended output frequency. When the PLL is not set up appropriately, the VCSO is forced to its upper or lower operating limit which is typically about 250 ppm above or below the VCSO center frequency no more than 500 ppm above or below . M2020/21 Datasheet Rev 4 of 10 Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400 Integrated Circuit Systems, Inc. M2020/21 VCSO BASED CLOCK PLL In normal phase-locked condition, the instantaneous phase error is measured by the phase detector and is converted to charge pump current pulses. These current pulses are then integrated by the external loop filter to create a VCSO control voltage. The loop filter acts as a low pass filter to remove unwanted reference clock jitter above a determined frequency or PLL bandwidth. For reference phase jitter frequencies within the loop bandwidth, phase jitter amplitude is passed on to the output clock according to the PLL loop frequency response curve. The relationship between the nominal VCSO center frequency Fvcso , the M divider, and the input reference frequency Fin is: Fvcso x Mfin -M-R TriState The TriState feature puts the LVPECL output driver into a high impedance state, effectively disconnecting the driver from the FOUT and nFOUT pins of the device. A logic 0 is then present on the clock net. The impedance of the clock net is then set to by the external circuit resistors. This is in distinction to a CMOS output in TriState, in which case the net goes to a high impedance and the logic value floats. The impedance level of the LVPECL TriState allows manufacturing In-circuit Test to drive the clock net with an external generator to validate the integrity of clock net and the clock load. The M2020/21 is available with a Hitless Switching feature that is enabled during device manufacturing. In addition, a Phase Build-out feature is also offered. These features are offered as device options and are specified by device order code. Refer to “Ordering Information” on pg. The Hitless Switching feature with or without Phase Build-out is designed for applications where switching occurs between two stable system reference clocks. It should not be used in loop timing applications, or when reference clock jitter is greater than 1 ns pk-pk. The Hitless Switching sequence is triggered by the LOL circuit, which is activated by a 4 ns phase transient. This magnitude of phase transient can generated by the CDR Clock & Data Recovery unit in loop timing mode, especially during a system jitter tolerance test. It can also be generated by some types of Stratum clock DPLLs digital PLL , especially those that do not include a post de-jitter APLL analog PLL . When the M2020/21 is operating in wide bandwidth mode NBW=0 , the optional Hitless Switching function puts the device into narrow bandwidth mode during the Hitless Switching sequence. This allows the PLL to lock the new input clock phase gradually. With proper configuration of the external loop filter, the output clock phase change complies with MTIE and TDEV specifications for GR-253 SONET and ITU G.813 SDH during input reference clock changes. The optional proprietary Phase Build-out PBO function enables the PLL to absorb most of the phase change of the input clock during reference switching. The PBO function selects a new VCSO clock edge for the PLL Phase Detector feedback clock, selecting the edge closest in phase to the new input clock phase. This reduces re-lock time, the generation of wander, and extra output clock cycles. The Hitless Switching and Phase Build-out functions are triggered by the LOL circuit. For proper operation, a low phase detector frequency must be avoided. See “Guidelines for Using LOL” on pg. 5 for information regarding the phase detector frequency. HS/PBO Sequence Trigger Mechanism The HS function or the combined HS/PBO function is armed after the device locks to the input clock reference. Once armed, HS is triggered by the occurance of a Loss of Lock condition. This would typically occur as a consequence of a clock reference failure, a clock failure upstream to the M2020/21, or a M2020/21 clock reference mux reselection. M2020/21 VCSO BASED CLOCK PLL HS/PBO Operation Once triggered, the following HS/PBO sequence occurs: The HS function disables the PLL Phase Detector and puts the device into NBW narrow bandwidth mode. The internal resistor Rin is changed to See External Loop Filter on pg. If included, the PBO function adds to builds out the phase in the clock feedback path in VCSO clock cycle increments to align the feedback clock with the new reference clock input phase. The PLL Phase Detector is enabled, allowing the PLL to re-lock. Once the PLL Phase Detector feedback and input clocks are locked to within 2 ns for eight consecutive cycles, a timer WBW timer for resuming wide bandwidth in 175 ns is started. The LOL pin will indicate lock status on a cycle-to-cycle basis and may be intermittent until PLL phase lock has fully stabilized. External Loop Filter To provide stable PLL operation, the M2020/21 requires the use of an external loop filter. This is provided via the provided filter pins see Figure The loop filter is implemented as a differential circuit to minimize system noise interference. RLOOP CLOOP RPOST RLOOP CLOOP RPOST CPOST OP_IN nOP_IN OP_OUT nOP_OUT nVC VC Figure 5 External Loop Filter PLL bandwidth is affected by loop filter component values, “M” and “Mfin” values, and the “PLL Loop Constants” listed in AC Characteristics on pg. The MR_SEL1 and MR_SEL0 settings can be used to actively change PLL loop bandwidth in a given application. See “M and R Divider Look-Up Table LUT ” on pg. See Table 7, Example Values for Loop Filter External Components, on pg. M2020/21 Datasheet Rev 6 of 10 Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400 Integrated Circuit Systems, Inc. M2020/21 VCSO BASED CLOCK PLL PLL Simulator Tool Available A free PC software utility is available on the ICS website The M2000 Timing Modules PLL Simulator is a downloadable application that simulates PLL jitter and wander transfer characteristics. This enables the user to set appropriate external loop component values in a given application. ORDERING INFORMATION Standard VCSO Output Frequencies MHz * Part Numbering Scheme Part Number: M202x- yz - xxx.xxxx Frequency Input Divider Option 0 = Mfin Divider selections of 32, 8, 4, or 1 = Mfin Divider selections of 16, 8, 4, or 1 Output type 1 = LVPECL For CML or LVDS clock output, consult factory Hitless Switching / Phase Build-out Options 1 = none 2 = Hitless Switching 3 = Hitless Switching with Phase Build-out Temperature “ - ” = 0 to +70 oC commercial I = - 40 to +85 oC industrial VCSO Frequency MHz See Table 12, right. Consult ICS for other frequencies. Table 12 Standard VCSO Output Frequencies Figure 9 Part Numbering Scheme Note * Fout can equal Fvcso divided by 1, 4, 8, or 32 Consult ICS for the availability of other VCSO frequencies. Example Part Numbers VCSO Frequency MHz Temperature Order Part Number commercial industrial commercial industrial M2020- 11- or M2021- 11- M2020- 11I622.0800 or M2021- 11I622.0800 M2020- 11- or M2021- 11- M2020- 11I625.0000 or M2021- 11I625.0000 Table 13 Example Part Numbers While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems ICS assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. M2020/21 Datasheet Rev 10 of 10 Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400

PDF Datasheet Preview

Integrated Circuit Systems, Inc.

M2020/21

VCSO BASED CLOCK PLL

The M2020/21 is a VCSO Voltage Controlled SAW Oscillator based clock jitter attenuator PLL designed for clock jitter attenuation and frequency translation. The device is ideal for generating the transmit reference clock for optical network systems supporting GB data rates. It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop timing mode. The M2020/21 module includes a proprietary SAW surface acoustic wave delay line as part of the VCSO. This results in a high frequency, high-Q, low phase noise oscillator that assures low intrinsic output jitter.

Integrated SAW surface acoustic wave delay line low phase jitter of < 0.5ps rms, typical 12kHz to 20MHz or 50kHz to 80MHz

Output frequencies of 15 to 700 MHz *

LVPECL clock output CML and LVDS options available

Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL

Loss of Lock LOL output pin Narrow Bandwidth control input NBW pin

Hitless Switching HS options with or without Phase Build-out PBO available for SONET GR-253 / SDH G.813 MTIE and TDEV compliance during reference clock reselection

Industrial temperature grade available

Single 3.3V power supply

Small 9 x 9 mm SMT surface mount package

PIN ASSIGNMENT 9 x 9 mm SMT
nDIF_REF1

DIF_REF1

REF_SEL
nDIF_REF0

DIF_REF0

P_SEL2

FIN_SEL1

FIN_SEL0 MR_SEL0 MR_SEL1

LOL NBW VCC DNC

M2020

M2021

Top View

P_SEL0 P_SEL1 nFOUT0 FOUT0 GND nFOUT1 FOUT1 VCC GND
nOP_IN

OP_OUT
nOP_OUT

OP_IN

Figure 1 Pin Assignment

Example I/O Clock Frequency Combinations Using M2020-11-622.0800 or M2021-11-622.0800

Input Reference Clock MHz

PLL Ratio

Pin Selectable

Output Clock MHz

M2020 M2021

M2020 M2021
32 or 16 8 4 1
An internal high "Q" SAW delay line provides low jitter signal performance and establishes the output frequency of the VCSO Voltage Controlled SAW Oscillator . In a given M2020/21 device, the VCSO center frequency is fixed. A common center frequency is 622.08MHz, for SONET for SDH optical network applications. The VCSO center frequency is specified at time of order see “Ordering Information” on pg. The VCSO has a guaranteed tuning range of ±120 ppm commercial temperature grade .

Pin selectable dividers are used within the PLL and for the output clock. This enables tailoring of device functionality and performance. The Mfin divider controls the overall PLL multiplication ratio and thus determines the input reference clock see Table 3, on pg. The M and R dividers control the phase detector frequency see Table The P divider scales the VCSO output enabling lower output frequency selections Table

The M2020/21 includes a Loss of Lock LOL indicator, which provides status information to system management software. A Narrow Bandwidth NBW control pin is provided as an additional mechanism for adjusting PLL loop bandwidth without affecting the phase detector frequency.

Options are available for Hitless Switching HS with or without Phase Build-out PBO . They provide SONET/SDH MTIE and TDEV compliance during a reference clock reselection.

Allowance for a single-ended input has been facilitated by a unique input resistor bias scheme, which is described next and shown in Figure

Input Reference Clocks

Two clock reference inputs and a selection mux are provided. Either reference clock input can accept a differential clock signal such as LVPECL or LVDS or a single-ended clock input LVCMOS or LVTTL on the non-inverting input .

A single-ended reference clock on the unselected reference input can cause an increase in output clock jitter. For this reason, differential reference inputs are preferred interference from a differential input on the non-selected input is minimal.

M2020/21

VCSO BASED CLOCK PLL

Configuration of a single-ended input has been facilitated by biasing nDIF_REF0 and nDEF_REF1 to Vcc/2, with to Vcc and to ground. The input clock structure, and how it is used with either LVCMOS/LVTTL inputs or a DC- coupled LVPECL clock, is shown in Figure

DIF_REF0

LVCMOS/

LVTTL
nDIF_REF0

DIF_REF1

LVPECL
nDIF_REF1

REF_SEL

Figure 4 Input Reference Clocks

M2020/21

Differential Inputs

Differential LVPECL inputs are connected to both reference input pins in the usual manner. The external load termination resistors shown in Figure 4 the and resistors is ideally suited for both AC and DC coupled LVPECL reference clock lines. These provide the load termination and the VTT bias voltage. Single-ended Inputs

Single-ended inputs LVCMOS or LVTTL are connected to the non-inverting reference input pin DIF_REF0 or DIF_REF1 . The inverting reference input pin nDIF_REF0 or nDIF_REF1 must be left unconnected.

In single-ended operation, when the unused inverting input pin nDIF_REF0 or nDEF_REF1 is left floating not connected , the input will self-bias at VCC/2.

PLL Operation

The M2020/21 is a complete clock PLL. It uses a phase detector and configurable dividers to synchronize the output of the VCSO with the selected reference clock.

The PLL will work correctly, meaning it will phase-lock the VCSO output to the input reference clock, when the internal phase detector inputs are able to run at the same frequency. This means the PLL dividers must be set appropriately and a suitable reference frequency must be chosen for the intended output frequency. When the PLL is not set up appropriately, the VCSO is forced to its upper or lower operating limit which is typically about 250 ppm above or below the VCSO center frequency no more than 500 ppm above or below .

M2020/21 Datasheet Rev
4 of 10

Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400

Integrated Circuit Systems, Inc.

M2020/21

VCSO BASED CLOCK PLL

In normal phase-locked condition, the instantaneous phase error is measured by the phase detector and is converted to charge pump current pulses. These current pulses are then integrated by the external loop filter to create a VCSO control voltage. The loop filter acts as a low pass filter to remove unwanted reference clock jitter above a determined frequency or PLL bandwidth. For reference phase jitter frequencies within the loop bandwidth, phase jitter amplitude is passed on to the output clock according to the PLL loop frequency response curve.

The relationship between the nominal VCSO center frequency Fvcso , the M divider, and the input reference frequency Fin is:

Fvcso
x Mfin
-M-R

TriState

The TriState feature puts the LVPECL output driver into a high impedance state, effectively disconnecting the driver from the FOUT and nFOUT pins of the device. A logic 0 is then present on the clock net. The impedance of the clock net is then set to by the external circuit resistors. This is in distinction to a CMOS output in TriState, in which case the net goes to a high impedance and the logic value floats. The impedance level of the LVPECL TriState allows manufacturing In-circuit Test to drive the clock net with an external generator to validate the integrity of clock net and the clock load.
The M2020/21 is available with a Hitless Switching feature that is enabled during device manufacturing. In addition, a Phase Build-out feature is also offered. These features are offered as device options and are specified by device order code. Refer to “Ordering Information” on pg.

The Hitless Switching feature with or without Phase Build-out is designed for applications where switching occurs between two stable system reference clocks. It should not be used in loop timing applications, or when reference clock jitter is greater than 1 ns pk-pk. The Hitless Switching sequence is triggered by the LOL circuit, which is activated by a 4 ns phase transient. This magnitude of phase transient can generated by the CDR Clock & Data Recovery unit in loop timing mode, especially during a system jitter tolerance test. It can also be generated by some types of Stratum clock DPLLs digital PLL , especially those that do not include a post de-jitter APLL analog PLL .

When the M2020/21 is operating in wide bandwidth mode NBW=0 , the optional Hitless Switching function puts the device into narrow bandwidth mode during the Hitless Switching sequence. This allows the PLL to lock the new input clock phase gradually. With proper configuration of the external loop filter, the output clock phase change complies with MTIE and TDEV specifications for GR-253 SONET and ITU G.813 SDH during input reference clock changes.

The optional proprietary Phase Build-out PBO function enables the PLL to absorb most of the phase change of the input clock during reference switching. The PBO function selects a new VCSO clock edge for the PLL Phase Detector feedback clock, selecting the edge closest in phase to the new input clock phase. This reduces re-lock time, the generation of wander, and extra output clock cycles.

The Hitless Switching and Phase Build-out functions are triggered by the LOL circuit. For proper operation, a low phase detector frequency must be avoided. See “Guidelines for Using LOL” on pg. 5 for information regarding the phase detector frequency.

HS/PBO Sequence Trigger Mechanism

The HS function or the combined HS/PBO function is armed after the device locks to the input clock reference. Once armed, HS is triggered by the occurance of a Loss of Lock condition. This would typically occur as a consequence of a clock reference failure, a clock failure upstream to the M2020/21, or a M2020/21 clock reference mux reselection.

M2020/21

VCSO BASED CLOCK PLL

HS/PBO Operation

Once triggered, the following HS/PBO sequence occurs:

The HS function disables the PLL Phase Detector and puts the device into NBW narrow bandwidth mode. The internal resistor Rin is changed to See External Loop Filter on pg.

If included, the PBO function adds to builds out the phase in the clock feedback path in VCSO clock cycle increments to align the feedback clock with the new reference clock input phase.

The PLL Phase Detector is enabled, allowing the PLL to re-lock.

Once the PLL Phase Detector feedback and input clocks are locked to within 2 ns for eight consecutive cycles, a timer WBW timer for resuming wide bandwidth in 175 ns is started.

The LOL pin will indicate lock status on a cycle-to-cycle basis and may be intermittent until PLL phase lock has fully stabilized.

External Loop Filter

To provide stable PLL operation, the M2020/21 requires
the use of an external loop filter. This is provided via the
provided filter pins see Figure The loop filter is
implemented as a differential circuit to minimize system
noise interference.

RLOOP CLOOP

RPOST

RLOOP CLOOP

RPOST

CPOST

OP_IN nOP_IN

OP_OUT nOP_OUT nVC VC

Figure 5 External Loop Filter

PLL bandwidth is affected by loop filter component values, “M” and “Mfin” values, and the “PLL Loop Constants” listed in AC Characteristics on pg.

The MR_SEL1 and MR_SEL0 settings can be used to actively change PLL loop bandwidth in a given application. See “M and R Divider Look-Up Table LUT ” on pg.

See Table 7, Example Values for Loop Filter External Components, on pg.

M2020/21 Datasheet Rev
6 of 10

Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400

Integrated Circuit Systems, Inc.

M2020/21

VCSO BASED CLOCK PLL

PLL Simulator Tool Available

A free PC software utility is available on the ICS website The M2000 Timing Modules PLL Simulator is a downloadable application that simulates PLL jitter and wander transfer characteristics. This enables the user to set appropriate external loop component values in a given application.
ORDERING INFORMATION

Standard VCSO Output Frequencies MHz *

Part Numbering Scheme

Part Number:

M202x- yz - xxx.xxxx

Frequency Input Divider Option 0 = Mfin Divider selections of 32, 8, 4, or 1 = Mfin Divider selections of 16, 8, 4, or 1

Output type 1 = LVPECL For CML or LVDS clock output, consult factory

Hitless Switching / Phase Build-out Options 1 = none 2 = Hitless Switching 3 = Hitless Switching with Phase Build-out

Temperature
“ - ” = 0 to +70 oC commercial I = - 40 to +85 oC industrial

VCSO Frequency MHz See Table 12, right. Consult ICS for other frequencies.

Table 12 Standard VCSO Output Frequencies

Figure 9 Part Numbering Scheme

Note * Fout can equal Fvcso divided by 1, 4, 8, or 32

Consult ICS for the availability of other VCSO frequencies.

Example Part Numbers

VCSO Frequency MHz Temperature

Order Part Number
commercial industrial commercial industrial

M2020- 11- or M2021- 11- M2020- 11I622.0800 or M2021- 11I622.0800 M2020- 11- or M2021- 11- M2020- 11I625.0000 or M2021- 11I625.0000

Table 13 Example Part Numbers

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems ICS assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.

M2020/21 Datasheet Rev
10 of 10

Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400

More datasheets: M2020-11-622.0800 | M2021-11-622.0800T | M2021-11-622.0800 | M2020-11-622.0800T | M2020-13-622.0800 | M2021-13-622.0800 | M2020-11-669.3266 | M2021-13-622.0800T | M2020-13I622.0800 | M2020-11-669.3266T

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Datasheet ID: M2020-11-625.0000T 637418