M2006-02-669.6429T

M2006-02-669.6429T Datasheet

M2006-02

Part	Datasheet
M2006-02-669.6429T	M2006-02-669.6429T (pdf)

Related Parts	Information
M2006-02-622.0800	M2006-02-622.0800
M2006-02-622.0800T	M2006-02-622.0800T
M2006-02-669.3266	M2006-02-669.3266
M2006-02-669.3266T	M2006-02-669.3266T
M2006-02-693.4830	M2006-02-693.4830
M2006-02-693.4830T	M2006-02-693.4830T
M2006-02-666.5143T	M2006-02-666.5143T
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M2006-02-690.5692T	M2006-02-690.5692T
M2006-02-666.5143	M2006-02-666.5143
M2006-02-625.0000T	M2006-02-625.0000T
M2006-02-690.5692	M2006-02-690.5692
M2006-02-669.6429	M2006-02-669.6429
M2006-02-644.5313	M2006-02-644.5313
M2006-02-625.0000	M2006-02-625.0000

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Integrated Circuit Systems, Inc. M2006-02 VCSO BASED FEC CLOCK PLL PIN ASSIGNMENT 9 x 9 mm SMT The M2006-02 is a VCSO Voltage Controlled SAW Oscillator based clock generator PLL designed for clock frequency translation and jitter attenuation. The device supports both forward and inverse FEC Forward Error Correction clock multiplication ratios. Multiplication ratios are pin-selected from pre-programming look-up tables. Pin-selectable PLL divider ratios support forward and inverse FEC ratio translation, including: • 255/238 OTU1 Mapping and 238/255 De-mapping • 255/237 OTU2 Mapping and 237/255 De-mapping • 255/236 OTU3 Mapping and 236/255 De-mapping Supports input reference and VCSO frequencies up to 700MHz, supports loop timing modes Specify VCSO frequency at time of order Low phase jitter < ps rms typical 12kHz to 20MHz or 50kHz to 80MHz Supports active switching between inverse-FEC and non-FEC clock ratios same VCSO center frequency Ideal for complex ratio FEC ratio translation* and for use with an unstable reference** i.e., similar to the M2006-12 - and pin-compatible - but without the Hitless Switching and Phase Build-out functions Commercial and Industrial temperature grades Single 3.3V power supply Small 9 x 9 mm SMT surface mount package FIN_SEL1 DIF_REF0 nDIF_REF0 FIN_SEL0 FEC_SEL0 FEC_SEL1 FEC_SEL2 FEC_SEL3 VCC DNC 31 M 2 0 6 - 0 2 15 Top View P0_SEL P1_SEL nFOUT0 FOUT0 GND nFOUT1 FOUT1 VCC GND nOP_IN OP_OUT nOP_OUT OP_IN Figure 1 Pin Assignment Example I/O Clock Frequency Combinations Using M2006-02-622.0800 and Inverse FEC Ratios FEC PLL Ratio Mfec / Rfec Base Input Rate 1 MHz Output Clock either output 1/1 238/255 237/255 236/255 Table 1 Example I/O Clock Frequency Combinations Note 1 Input reference clock can be the base frequency shown divided by “Mfin” as shown in Table 3 on pg. REF_SEL DIF_REF1 nDIF_REF1 Note * Complex ratio FEC ratio translation typically results in low phase detector frequencies. Note ** An unstable reference which results in phase detector jitter beyond 2 ns under normal operating conditions SIMPLIFIED BLOCK DIAGRAM For example, the M2006-02-622.0800 see “Ordering Information” on pg. 8 has a 622.08MHz VCSO frequency: • The inverse FEC PLL ratios at top of Table 4 enable the M2006-02-622.0800 to accept “base” input reference frequencies of and 622.08MHz. • The Mfin feedback divider enables the actual input reference clock to be the “base” input frequency divided by 1, 4, 8, or Therefore, for the base input frequency of 622.08MHz, the actual input reference clock frequencies can be and 19.44MHz. See Table 3 on pg. M2006-02 Datasheet Rev 3 of 8 Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400 Integrated Circuit Systems, Inc. The PLL The PLL uses a phase detector and configurable dividers to synchronize the output of the VCSO with selected reference clock. The “Mfin Divider” and “Mfec Divider” divide the VCSO frequency, feeding the result into the phase detector. The selected input reference clock is divided by the “Rfec Divider”. The result is fed into the other input of the phase detector. The phase detector compares its two inputs. It then outputs pulses to the loop filter as needed to increase or decrease the VCSO frequency and thereby match and lock the divider output’s frequency and phase to those of the input reference clock. Due to the narrow tuning range of the VCSO +200ppm , appropriate selection of all of the following are required for the PLL be able to lock VCSO center frequency, input frequency, and divider selections. Maintaining PLL Lock The narrow tuning range of the VCSO requires that the input reference frequency must remain suitable for the current look-up table selection. For example, when switching between “Inverse FEC ratio” and “Non-FEC ratio” look-up table selections see Table 4 on pg. 3 , the input reference frequency must change accordingly in order for the PLL to lock. An out-of-lock condition due to an inappropriate configuration will typically result in the VCSO operating at its lower or upper frequency rail, which is approximately 200ppm above or below the nominal VCSO center frequency. M2006-02 VCSO BASED FEC CLOCK PLL Relationship Among Frequencies and Dividers The VCSO center frequency must be specified at time of order. The relationship between the VCSO Fvcso frequency, the Mfin divider, the Mfec divider, the Rfec divider, and the input reference frequency Fin is: Fvcso x Mfin -M-----f--e----cRfec As an example, for the M2006-02-622.0800, the non-FEC and inverse-FEC PLL ratios in Table 4 enable use with these corresponding input reference frequencies: M2006-02-622.0800 VCSO Clock Frequency MHz ÷ FEC Ratio M2006-02-622.0800 Base Input Ref. = Frequency MHz 1 238 / 255 237 / 255 236 / 255 Table 6 Example FEC PLL Rations and Input Reference Frequencies Note 1 Input reference clock “Fin” can be the base frequency shown divided by “Mfin” as shown in Table 3 on pg. Outputs The M2006-02 provides a total of two differential LVPECL output pairs FOUT1 and FOUT0. Because each output pair has its own P divider, the FOUT1 pair and the FOUT0 can output the two different frequencies at the same time. For example, FOUT1 can output 155.52MHz while FOUT0 outputs 622.08MHz. Any unused output should be left unconnected floating in the system application. This will minimize output switching current and therefore minimize noise modulation of the VCSO. M2006-02 Datasheet Rev 4 of 8 Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400 ORDERING INFORMATION Part Numbering Scheme Part Number: Device Number M2006- 02 - xxx.xxxx Standard VCSO Output Frequencies MHz * Consult ICS for the availablity of other VCSO frequencies Temperature “ - ” = 0 to +70 oC commercial I = - 40 to +85 oC industrial VCSO Frequency MHz See Table 11, right. Consult ICS for other frequencies. Figure 8 Part Numbering Scheme Table 11 Standard VCSO Output Frequencies MHz Note * Fout can equal Fvcso divided by 1 or 4 Consult ICS for the availability of other PLL frequencies. Example Part Numbers PLL Frequency MHz Temperature commercial industrial commercial industrial commercial industrial commercial industrial Order Part Number M2006-02- M2006-02I M2006-02- M2006-02I M2006-02- M2006-02I M2006-02- M2006-02I Table 12 Example Part Numbers While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems ICS assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. M2006-02 Datasheet Rev 8 of 8 Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400

PDF Datasheet Preview

Integrated Circuit Systems, Inc.

M2006-02

VCSO BASED FEC CLOCK PLL

PIN ASSIGNMENT 9 x 9 mm SMT

The M2006-02 is a VCSO Voltage Controlled SAW Oscillator based clock generator PLL designed for clock frequency translation and jitter attenuation. The device supports both forward and inverse FEC Forward Error Correction clock multiplication ratios. Multiplication ratios are
pin-selected from pre-programming look-up tables.

Pin-selectable PLL divider ratios support forward and inverse FEC ratio translation, including:
• 255/238 OTU1 Mapping and 238/255 De-mapping
• 255/237 OTU2 Mapping and 237/255 De-mapping
• 255/236 OTU3 Mapping and 236/255 De-mapping

Supports input reference and VCSO frequencies up to 700MHz, supports loop timing modes Specify VCSO frequency at time of order

Low phase jitter < ps rms typical 12kHz to 20MHz or 50kHz to 80MHz

Supports active switching between inverse-FEC and non-FEC clock ratios same VCSO center frequency

Ideal for complex ratio FEC ratio translation* and for use with an unstable reference** i.e., similar to the M2006-12 - and pin-compatible - but without the Hitless Switching and Phase Build-out functions

Commercial and Industrial temperature grades

Single 3.3V power supply

Small 9 x 9 mm SMT surface mount package

FIN_SEL1

DIF_REF0
nDIF_REF0

FIN_SEL0 FEC_SEL0 FEC_SEL1 FEC_SEL2 FEC_SEL3

VCC DNC
31 M 2 0 6 - 0 2 15

Top View

P0_SEL P1_SEL nFOUT0 FOUT0 GND nFOUT1 FOUT1 VCC GND
nOP_IN

OP_OUT
nOP_OUT

OP_IN

Figure 1 Pin Assignment

Example I/O Clock Frequency Combinations Using M2006-02-622.0800 and Inverse FEC Ratios

FEC PLL Ratio Mfec / Rfec

Base Input Rate 1 MHz

Output Clock either output
1/1 238/255 237/255 236/255

Table 1 Example I/O Clock Frequency Combinations

Note 1 Input reference clock can be the base frequency shown divided by “Mfin” as shown in Table 3 on pg.

REF_SEL

DIF_REF1
nDIF_REF1

Note * Complex ratio FEC ratio translation typically results in low phase detector frequencies.

Note ** An unstable reference which results in phase detector jitter beyond 2 ns under normal operating conditions

SIMPLIFIED BLOCK DIAGRAM
For example, the M2006-02-622.0800 see “Ordering Information” on pg. 8 has a 622.08MHz VCSO frequency:
• The inverse FEC PLL ratios at top of Table 4 enable
the M2006-02-622.0800 to accept “base” input reference frequencies of and 622.08MHz.
• The Mfin feedback divider enables the actual input
reference clock to be the “base” input frequency divided by 1, 4, 8, or Therefore, for the base input frequency of 622.08MHz, the actual input reference clock frequencies can be and 19.44MHz. See Table 3 on pg.

M2006-02 Datasheet Rev
3 of 8

Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400

Integrated Circuit Systems, Inc.

The PLL

The PLL uses a phase detector and configurable dividers to synchronize the output of the VCSO with selected reference clock.

The “Mfin Divider” and “Mfec Divider” divide the VCSO frequency, feeding the result into the phase detector.

The selected input reference clock is divided by the “Rfec Divider”. The result is fed into the other input of the phase detector.

The phase detector compares its two inputs. It then outputs pulses to the loop filter as needed to increase or decrease the VCSO frequency and thereby match and lock the divider output’s frequency and phase to those of the input reference clock.

Due to the narrow tuning range of the VCSO +200ppm , appropriate selection of all of the following are required for the PLL be able to lock VCSO center frequency, input frequency, and divider selections.

Maintaining PLL Lock The narrow tuning range of the VCSO requires that the input reference frequency must remain suitable for the current look-up table selection. For example, when switching between “Inverse FEC ratio” and “Non-FEC ratio” look-up table selections see Table 4 on pg. 3 , the input reference frequency must change accordingly in order for the PLL to lock.

An out-of-lock condition due to an inappropriate configuration will typically result in the VCSO operating at its lower or upper frequency rail, which is approximately 200ppm above or below the nominal VCSO center frequency.

M2006-02

VCSO BASED FEC CLOCK PLL

Relationship Among Frequencies and Dividers

The VCSO center frequency must be specified at time of order. The relationship between the VCSO Fvcso frequency, the Mfin divider, the Mfec divider, the Rfec divider, and the input reference frequency Fin is:

Fvcso
x Mfin
-M-----f--e----cRfec

As an example, for the M2006-02-622.0800, the non-FEC and inverse-FEC PLL ratios in Table 4 enable use with these corresponding input reference frequencies:

M2006-02-622.0800

VCSO Clock

Frequency MHz ÷

FEC Ratio

M2006-02-622.0800

Base Input Ref. = Frequency MHz 1
238 / 255 237 / 255
236 / 255

Table 6 Example FEC PLL Rations and Input Reference Frequencies Note 1 Input reference clock “Fin” can be the base frequency
shown divided by “Mfin” as shown in Table 3 on pg.

Outputs

The M2006-02 provides a total of two differential LVPECL output pairs FOUT1 and FOUT0. Because each output pair has its own P divider, the FOUT1 pair and the FOUT0 can output the two different frequencies at the same time. For example, FOUT1 can output 155.52MHz while FOUT0 outputs 622.08MHz.

Any unused output should be left unconnected floating in the system application. This will minimize output switching current and therefore minimize noise modulation of the VCSO.

M2006-02 Datasheet Rev
4 of 8

Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400
ORDERING INFORMATION

Part Numbering Scheme

Part Number:

Device Number

M2006- 02 - xxx.xxxx

Standard VCSO Output Frequencies MHz *

Consult ICS for the availablity of other VCSO frequencies

Temperature
“ - ” = 0 to +70 oC commercial I = - 40 to +85 oC industrial

VCSO Frequency MHz See Table 11, right. Consult ICS for other frequencies.

Figure 8 Part Numbering Scheme

Table 11 Standard VCSO Output Frequencies MHz Note * Fout can equal Fvcso divided by 1 or 4

Consult ICS for the availability of other PLL frequencies.

Example Part Numbers

PLL Frequency MHz

Temperature
commercial industrial commercial industrial commercial industrial commercial industrial

Order Part Number M2006-02- M2006-02I M2006-02- M2006-02I M2006-02- M2006-02I M2006-02- M2006-02I

Table 12 Example Part Numbers

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems ICS assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.

M2006-02 Datasheet Rev
8 of 8

Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400

More datasheets: 76650-0220 | MDM-37PH003M7 | M2006-02-622.0800 | M2006-02-622.0800T | M2006-02-669.3266 | M2006-02-669.3266T | M2006-02-693.4830 | M2006-02-693.4830T | M2006-02-666.5143T | M2006-02-644.5313T

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Datasheet ID: M2006-02-669.6429T 637416