M1033-16-155.5200

M1033-16-155.5200 Datasheet

M1033/34

Part	Datasheet
M1033-16-155.5200	M1033-16-155.5200 (pdf)

Related Parts	Information
M1033-16-155.5200T	M1033-16-155.5200T

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Integrated Circuit Systems, Inc. M1033/34 VCSO BASED CLOCK PLL WITH AUTOSWITCH The M1033/34 is a VCSO Voltage Controlled SAW Oscillator based clock jitter attenuator PLL designed for clock jitter attenuation and frequency translation. The device is ideal for generating the transmit reference clock for optical network systems supporting up to 2.5Gb data rates. It can serve to jitter attenuate a stratum reference clock or a recovered clock in loop timing mode. The M1033/34 module includes a proprietary SAW surface acoustic wave delay line as part of the VCSO. This results in a high frequency, high-Q, low phase noise oscillator that assures low intrinsic output jitter. Integrated SAW delay line low phase jitter of < 0.5ps rms, typical 12kHz to 20MHz Output frequencies of to 175 MHz Specify VCSO output frequency at time of order LVPECL clock output CML and LVDS options available Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL Loss of Reference LOR output pin Narrow Bandwidth control input NBW pin AutoSwitch AUTO pin - automatic non-revertive reference clock reselection upon clock failure Acknowledge pin REF_ACK pin indicates the actively selected reference input Phase Build-out only upon MUX reselection option PBOM Pin-selectable feedback and reference divider ratios Single 3.3V power supply Small 9 x 9 mm SMT surface mount package SIMPLIFIED BLOCK DIAGRAM PIN ASSIGNMENT 9 x 9 mm SMT nDIF_REF1 DIF_REF1 REF_SEL nDIF_REF0 DIF_REF0 MR_SEL3 MR_SEL2 MR_SEL0 MR_SEL1 LOR NBW VCC DNC M1033 M1034 Top View P_SEL0 P_SEL1 nFOUT FOUT GND REF_ACK AUTO VCC GND nOP_IN OP_OUT nOP_OUT OP_IN Figure 1 Pin Assignment Example I/O Clock Frequency Combinations Using M1033-11-155.5200 or M1034-11-155.5200 Input Reference Clock MHz PLL Ratio Pin Selectable Output Clock MHz Pin Selectable Tables 3 and 4 provide example Fin and phase detector frequencies with 155.52MHz VCSO devices M1033-11-155.5200 and M1034-11-155.5200 . See “Ordering Information” on pg. M1034 M/R Divider LUT Total MR_SEL3:0 M Div R Div PLL Ratio Fin for 155.52MHz VCSO MHz Phase Det. Freq. for 155.52MHz VCSO MHz 0000 4 1 0 1 16 4 0 1 0 64 16 0 1 256 64 0100 2 1 0101 8 4 0 1 0 32 16 0 1 128 64 1000 1 1001 4 1 0 1 0 16 1 0 1 64 1 0 Test Mode1 N/A 1 0 1 4 1 0 4 16 1 16 64 Table 4 M1034 M/R Divider LUT Note 1 Factory test mode do not use. M1033/34 Datasheet Rev 3 of 14 Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400 Integrated Circuit Systems, Inc. General Guidelines for M and R Divider Selection General guidelines for M/R divider selection see following pages for more detail : • A lower phase detector frequency should be used for loop timing applications to assure PLL tracking, especially during GR-253 jitter tolerance testing. The recommended maximum phase detector frequency for loop timing mode is 19.44MHz. P Divider Look-Up Table LUT The P_SEL1 and P_SEL0 pins select the post-PLL divider value P. The output frequency of the SAW can be divided by 1 or 2 or the output can be TriStated as specified in Table P_SEL1:0 00 01 10 11 P Value M1033-155.5200 or M1034-155.5200 Output Frequency MHz TriState the M1034-11-155.5200. “Ordering Information”, pg. Due to the narrow tuning range of the VCSO +200ppm , appropriate selection of all of the following are required for the PLL be able to lock VCSO center frequency, input frequency, and divider selections. Post-PLL Divider The M1033/34 features a post-PLL P divider. By using the P Divider, the device’s output frequency Fout can be the VCSO center frequency Fvcso or 1/2 Fvcso. The P_SEL pin selects the value for the P divider logic 1 sets P to 2, logic 0 sets P to See Table 5 on pg. When the P divider is included, the complete relation- ship for the output frequency Fout is defined as: Fout = --F----v---c---s---o---- = Fin x ------M----------- Due to the narrow tuning range of the VCSO +200ppm , appropriate selection of all of the following are required for the PLL be able to lock VCSO center frequency, input frequency, and divider selections. M1033/34 Datasheet Rev 5 of 14 Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400 Integrated Circuit Systems, Inc. TriState The TriState feature puts the LVPECL output driver into a high impedance state, effectively disconnecting the driver from the FOUT and nFOUT pins of the device. In application, the voltage of FOUT and nFOUT will be VTT, the LVPECL termination voltage, due to the external output termination resistors for LVPECL, this is an undefined logic condition . The impedance of the clock net is also due to the external circuit resistors this is in distinction to a CMOS output in TriState, which goes to a high impedance and the logic value floats. The impedance level of the LVPECL TriState allows manufacturing In-circuit Test to drive the clock net with an external generator to validate the integrity of clock net and the clock load. Any unused output single-ended or differential should be left unconnected floating in system application. This minimizes output switching current and therefore minimizes noise modulation of the VCSO. Loss of Reference Indicator LOR Output Pin Each input reference port DIF_REF0 and DIF_REF1 has an internal dedicated clock activity monitor circuit. The output from this circuit for the currently selected port is provided at device pin LOR, and is also used by the AutoSwitch circuit when the device is in Auto mode. The clock activity monitor circuits are clocked by the PLL phase detector feedback clock. The LOR output is asserted high if there are three consecutive feedback clock edges without any reference clock edges in both cases, either a negative or positive transition is counted as an “edge” . The LOR output will otherwise be low. The activity monitor does not flag excessive reference transitions in an phase detector observation interval as an error. The monitor only distinguishes between transitions occurring and no transitions occurring. Reference Acknowledgement REF_ACK Output The REF_ACK reference acknowledgement pin outputs the value of the reference clock input that is routed to the phase detector. Logic 1 indicates input pair 1 nDIF_REF1, DIF_REF1 logic 0 indicates input pair 0 nDIF_REF0, DIF_REF0 . The REF_ACK indicator is an LVCMOS output. M1033/34 VCSO BASED CLOCK PLL WITH AUTOSWITCH AutoSwitch AUTO Reference Clock Reselection This device offers an automatic reference clock reselection feature for switching input reference clocks upon a reference clock failure. The automatic reference clock reselection feature, known as AutoSwitch, is controlled by the device application system through device pins. When the LOR output is low, the AUTO input pin can be set high by the system to place the device into AutoSwitch automatic reselection mode. Once in AutoSwitch mode, when LOR goes high due to a fault in the selected reference clock , the input clock reference is automatically reselected by the internal AutoSwitch circuit, as indicated by the state change of the REF_ACK output. Automatic clock reselection is made only once it is non-revertive each time the AutoSwitch circuit is armed. Re-arming of automatic mode requires placing the device into Manual Selection mode AUTO pin low before returning to AutoSwitch mode AUTO pin high . A more detailed discussion is provided in the following section. M1033/34 Datasheet Rev 6 of 14 Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400 Integrated Circuit Systems, Inc. M1033/34 VCSO BASED CLOCK PLL WITH AUTOSWITCH Using the AutoSwitch Feature See also Table 6, Example AutoSwitch Sequence. In application, the system must be powered up with the device in Manual Select mode AUTO pin is set low . The activity monitor output LOR should then be polled to verify that the input clock reference is valid. REF_SEL should be set to select the desired input clock reference. This selection determines the reference clock to be used in Manual Select mode and the initial reference clock used in AutoSwitch mode. Sufficient time must be allocated for the PLL to acquire lock to the selected input reference. In most system configurations, where loop bandwidth is in the range of 100-1000 Hz and damping factor below 10, a delay of 500 ms should be sufficient. The REF_SEL input state must be maintained when switching to AutoSwitch mode AUTO pin high and in addition must still be maintained until a reference fault occurs. If a reference fault occurs on the selected reference input, the LOR output goes high and the input reference is automatically reselected. The REF_ACK output always indicates the reference selection status and the LOR output always indicated the selected input reference clock status. A successful automatic reselection is indicated by a change of state of the REF_ACK output. If an automatic reselection is made to a non-active reference clock input, the REF_ACK output will change state and both LOR outputs will remain high. No further automatic reselection is made by the device only one reselection is made each time the AutoSwitch mode is armed by the system. AutoSwitch mode is re-armed by the system by placing the device into Manual Select mode AUTO pin low and then into AutoSwitch mode again AUTO pin high . Following an automatic reselection and prior to selecting Manual Select mode AUTO pin low , the REF_SEL pin has no control of reference selection. To prevent an unintentional reference reselection, AutoSwitch mode must not be re-enabled until the desired state of the REF_SEL pin is set and the LOR output is low. It is recommended to delay the re-arming of AutoSwitch mode, following an automatic reselection, to ensure the PLL is fully locked on the new reference. Example AutoSwitch Sequence 0 = Low 1 = High. Example with REF_SEL initially set to 0 i.e., DIF_REF0 selected REF_SEL Selected REF_ACK AUTO LOR Conditions ORDERING INFORMATION Standard VCSO Output Frequencies MHz * Part Numbering Scheme Part Number: M103x- 1z - xxx.xxxx Frequency Input Divider Option 3 = Fin can equal Fvcso divided by 8, 2, or 1 4 = Fin can equal Fvcso divided by 4, 2, or 1 Output type 1 = LVPECL For CML or LVDS clock output, consult factory Phase Build-out Option, PBOM, mux triggered only 1 = PBOM not enabled 6 = PBOM enabled Temperature “ - ” = 0 to +70 oC commercial I = - 40 to +85 oC industrial Table 12 Standard VCSO Output Frequencies MHz VCSO Frequency MHz See Table 12, right. Consult ICS for other frequencies. Figure 9 Part Numbering Scheme Note * Fout can equal Fvcso divided by 1 or 2 Consult ICS for the availability of other VCSO frequencies. Example Part Numbers VCSO Frequency MHz Temperature Order Part Number Examples commercial industrial commercial industrial M1033- 11- or M1034- 11- M1033- 11I155.5200 or M1034- 11I155.5200 M1033- 11- or M1034- 11- M1033- 11I156.2500 or M1034- 11I156.2500 Table 13 Example Part Numbers While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems ICS assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. M1033/34 Datasheet Rev 14 of 14 Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400

PDF Datasheet Preview

Integrated Circuit Systems, Inc.

M1033/34

VCSO BASED CLOCK PLL WITH AUTOSWITCH

The M1033/34 is a VCSO Voltage Controlled SAW Oscillator based clock jitter attenuator PLL designed for clock jitter attenuation and frequency translation. The device is ideal for generating the transmit reference clock for optical network systems supporting up to 2.5Gb data rates. It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop timing mode. The M1033/34 module includes a proprietary SAW surface acoustic wave delay line as part of the VCSO. This results in a high frequency, high-Q, low phase noise oscillator that assures low intrinsic output jitter.

Integrated SAW delay line low phase jitter of < 0.5ps rms, typical 12kHz to 20MHz

Output frequencies of to 175 MHz Specify VCSO output frequency at time of order

LVPECL clock output CML and LVDS options available

Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL

Loss of Reference LOR output pin Narrow Bandwidth control input NBW pin

AutoSwitch AUTO pin - automatic non-revertive reference clock reselection upon clock failure

Acknowledge pin REF_ACK pin indicates the actively selected reference input

Phase Build-out only upon MUX reselection option PBOM

Pin-selectable feedback and reference divider ratios

Single 3.3V power supply

Small 9 x 9 mm SMT surface mount package

SIMPLIFIED BLOCK DIAGRAM

PIN ASSIGNMENT 9 x 9 mm SMT
nDIF_REF1

DIF_REF1

REF_SEL
nDIF_REF0

DIF_REF0

MR_SEL3

MR_SEL2 MR_SEL0 MR_SEL1

LOR NBW VCC DNC

M1033

M1034

Top View

P_SEL0 P_SEL1 nFOUT FOUT GND REF_ACK AUTO VCC GND
nOP_IN

OP_OUT
nOP_OUT

OP_IN

Figure 1 Pin Assignment

Example I/O Clock Frequency Combinations Using M1033-11-155.5200 or M1034-11-155.5200

Input Reference Clock MHz

PLL Ratio

Pin Selectable

Output Clock MHz

Pin Selectable
Tables 3 and 4 provide example Fin and phase detector frequencies with 155.52MHz VCSO devices M1033-11-155.5200 and M1034-11-155.5200 . See “Ordering Information” on pg.

M1034 M/R Divider LUT

Total MR_SEL3:0 M Div R Div PLL

Ratio

Fin for 155.52MHz VCSO MHz

Phase Det. Freq. for
155.52MHz VCSO MHz
0000 4 1
0 1 16 4
0 1 0 64 16
0 1 256 64
0100 2 1
0101 8 4
0 1 0 32 16
0 1 128 64
1000 1
1001 4
1 0 1 0 16
1 0 1 64
1 0 Test Mode1 N/A
1 0 1 4
1 0 4 16
1 16 64

Table 4 M1034 M/R Divider LUT

Note 1 Factory test mode do not use.

M1033/34 Datasheet Rev
3 of 14

Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400

Integrated Circuit Systems, Inc.

General Guidelines for M and R Divider Selection

General guidelines for M/R divider selection see following pages for more detail :
• A lower phase detector frequency should be used for
loop timing applications to assure PLL tracking, especially during GR-253 jitter tolerance testing. The recommended maximum phase detector frequency for loop timing mode is 19.44MHz.

P Divider Look-Up Table LUT

The P_SEL1 and P_SEL0 pins select the post-PLL divider value P. The output frequency of the SAW can be divided by 1 or 2 or the output can be TriStated as specified in Table

P_SEL1:0
00 01 10 11

P Value

M1033-155.5200 or M1034-155.5200

Output Frequency MHz

TriState
the M1034-11-155.5200. “Ordering Information”, pg.

Due to the narrow tuning range of the VCSO +200ppm , appropriate selection of all of the following are required for the PLL be able to lock VCSO center frequency, input frequency, and divider selections.

Post-PLL Divider

The M1033/34 features a post-PLL P divider. By using the P Divider, the device’s output frequency Fout can be the VCSO center frequency Fvcso or 1/2 Fvcso.

The P_SEL pin selects the value for the P divider logic 1 sets P to 2, logic 0 sets P to See Table 5 on pg.

When the P divider is included, the complete relation-
ship for the output frequency Fout is defined as:

Fout = --F----v---c---s---o---- = Fin x ------M-----------

Due to the narrow tuning range of the VCSO
+200ppm , appropriate selection of all of the following
are required for the PLL be able to lock VCSO center
frequency, input frequency, and divider selections.

M1033/34 Datasheet Rev
5 of 14

Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400

Integrated Circuit Systems, Inc.

TriState

The TriState feature puts the LVPECL output driver into a high impedance state, effectively disconnecting the driver from the FOUT and nFOUT pins of the device. In application, the voltage of FOUT and nFOUT will be VTT, the LVPECL termination voltage, due to the external output termination resistors for LVPECL, this is an undefined logic condition . The impedance of the clock net is also due to the external circuit resistors this is in distinction to a CMOS output in TriState, which goes to a high impedance and the logic value floats. The impedance level of the LVPECL TriState allows manufacturing In-circuit Test to drive the clock net with an external generator to validate the integrity of clock net and the clock load.

Any unused output single-ended or differential should be left unconnected floating in system application. This minimizes output switching current and therefore minimizes noise modulation of the VCSO.

Loss of Reference Indicator LOR Output Pin

Each input reference port DIF_REF0 and DIF_REF1 has an internal dedicated clock activity monitor circuit. The output from this circuit for the currently selected port is provided at device pin LOR, and is also used by the AutoSwitch circuit when the device is in Auto mode. The clock activity monitor circuits are clocked by the PLL phase detector feedback clock. The LOR output is asserted high if there are three consecutive feedback clock edges without any reference clock edges in both cases, either a negative or positive transition is counted as an “edge” . The LOR output will otherwise be low. The activity monitor does not flag excessive reference transitions in an phase detector observation interval as an error. The monitor only distinguishes between transitions occurring and no transitions occurring.

Reference Acknowledgement REF_ACK Output The REF_ACK reference acknowledgement pin outputs the value of the reference clock input that is routed to the phase detector. Logic 1 indicates input pair 1 nDIF_REF1, DIF_REF1 logic 0 indicates input pair 0 nDIF_REF0, DIF_REF0 . The REF_ACK indicator is an LVCMOS output.

M1033/34

VCSO BASED CLOCK PLL WITH AUTOSWITCH

AutoSwitch AUTO Reference Clock Reselection

This device offers an automatic reference clock reselection feature for switching input reference clocks upon a reference clock failure. The automatic reference clock reselection feature, known as AutoSwitch, is controlled by the device application system through device pins. When the LOR output is low, the AUTO input pin can be set high by the system to place the device into AutoSwitch automatic reselection mode. Once in AutoSwitch mode, when LOR goes high due to a fault in the selected reference clock , the input clock reference is automatically reselected by the internal AutoSwitch circuit, as indicated by the state change of the REF_ACK output. Automatic clock reselection is made only once it is non-revertive each time the AutoSwitch circuit is armed. Re-arming of automatic mode requires placing the device into Manual Selection mode AUTO pin low before returning to AutoSwitch mode AUTO pin high . A more detailed discussion is provided in the following section.

M1033/34 Datasheet Rev
6 of 14

Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400

Integrated Circuit Systems, Inc.

M1033/34

VCSO BASED CLOCK PLL WITH AUTOSWITCH

Using the AutoSwitch Feature

See also Table 6, Example AutoSwitch Sequence.

In application, the system must be powered up with the device in Manual Select mode AUTO pin is set low . The activity monitor output LOR should then be polled to verify that the input clock reference is valid. REF_SEL should be set to select the desired input clock reference. This selection determines the reference clock to be used in Manual Select mode and the initial reference clock used in AutoSwitch mode. Sufficient time must be allocated for the PLL to acquire lock to the selected input reference. In most system configurations, where loop bandwidth is in the range of 100-1000 Hz and damping factor below 10, a delay of 500 ms should be sufficient. The REF_SEL input state must be maintained when switching to AutoSwitch mode AUTO pin high and in addition must still be maintained until a reference fault occurs. If a reference fault occurs on the selected reference input, the LOR output goes high and the input reference is automatically reselected. The REF_ACK output always
indicates the reference selection status and the LOR output always indicated the selected input reference clock status. A successful automatic reselection is indicated by a change of state of the REF_ACK output.

If an automatic reselection is made to a non-active reference clock input, the REF_ACK output will change state and both LOR outputs will remain high.

No further automatic reselection is made by the device only one reselection is made each time the AutoSwitch mode is armed by the system. AutoSwitch mode is re-armed by the system by placing the device into Manual Select mode AUTO pin low and then into AutoSwitch mode again AUTO pin high . Following an automatic reselection and prior to selecting Manual Select mode AUTO pin low , the REF_SEL pin has no control of reference selection. To prevent an unintentional reference reselection, AutoSwitch mode must not be re-enabled until the desired state of the REF_SEL pin is set and the LOR output is low. It is recommended to delay the re-arming of AutoSwitch mode, following an automatic reselection, to ensure the PLL is fully locked on the new reference.

Example AutoSwitch Sequence
0 = Low 1 = High. Example with REF_SEL initially set to 0 i.e., DIF_REF0 selected

REF_SEL Selected REF_ACK AUTO LOR Conditions
ORDERING INFORMATION

Standard VCSO Output Frequencies MHz *

Part Numbering Scheme

Part Number:

M103x- 1z - xxx.xxxx

Frequency Input Divider Option
3 = Fin can equal Fvcso divided by 8, 2, or 1 4 = Fin can equal Fvcso divided by 4, 2, or 1

Output type 1 = LVPECL For CML or LVDS clock output, consult factory

Phase Build-out Option, PBOM, mux triggered only 1 = PBOM not enabled 6 = PBOM enabled

Temperature
“ - ” = 0 to +70 oC commercial I = - 40 to +85 oC industrial

Table 12 Standard VCSO Output Frequencies MHz

VCSO Frequency MHz See Table 12, right. Consult ICS for other frequencies.

Figure 9 Part Numbering Scheme

Note * Fout can equal Fvcso divided by 1 or 2

Consult ICS for the availability of other VCSO frequencies.

Example Part Numbers

VCSO Frequency MHz Temperature

Order Part Number Examples
commercial industrial commercial industrial

M1033- 11- or M1034- 11- M1033- 11I155.5200 or M1034- 11I155.5200 M1033- 11- or M1034- 11- M1033- 11I156.2500 or M1034- 11I156.2500

Table 13 Example Part Numbers

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems ICS assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.

M1033/34 Datasheet Rev
14 of 14

Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400

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Datasheet ID: M1033-16-155.5200 637413