M1026-13-155.5200

M1026-13-155.5200 Datasheet

M1025/26

Part	Datasheet
M1026-13-155.5200	M1026-13-155.5200 (pdf)

Related Parts	Information
M1026-13-155.5200T	M1026-13-155.5200T

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Integrated Circuit Systems, Inc. M1025/26 VCSO BASED CLOCK PLL WITH AUTOSWITCH The M1025/26 is a VCSO Voltage Controlled SAW Oscillator based clock jitter attenuator PLL designed for clock jitter attenuation and frequency translation. The device is ideal for generating the transmit reference clock for optical network systems supporting up to 2.5Gb data rates. It can serve to jitter attenuate a stratum reference clock or a recovered clock in loop timing mode. The M1025/26 module includes a proprietary SAW surface acoustic wave delay line as part of the VCSO. This results in a high frequency, high-Q, low phase noise oscillator that assures low intrinsic output jitter. PIN ASSIGNMENT 9 x 9 mm SMT nDIF_REF1 DIF_REF1 REF_SEL nDIF_REF0 DIF_REF0 MR_SEL3 MR_SEL2 MR_SEL0 MR_SEL1 LOL NBW VCC DNC 30 31 M1025 16 15 M1026 Top View P_SEL0 P_SEL1 nFOUT FOUT GND REF_ACK AUTO VCC GND nOP_IN OP_OUT nOP_OUT OP_IN Integrated SAW delay line low phase jitter of < 0.5ps rms, typical 12kHz to 20MHz Output frequencies of to 175 MHz Specify VCSO output frequency at time of order LVPECL clock output CML and LVDS options available Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL Loss of Lock LOL output pin Narrow Bandwidth control input NBW pin AutoSwitch AUTO pin - automatic non-revertive reference clock reselection upon clock failure Acknowledge pin REF_ACK pin indicates the actively selected reference input Hitless Switching HS options with or without Phase Build-out PBO to enable SONET GR-253 /SDH G.813 MTIE and TDEV compliance during reselection Pin-selectable feedback and reference divider ratios Single 3.3V power supply Small 9 x 9 mm SMT surface mount package SIMPLIFIED BLOCK DIAGRAM Figure 1 Pin Assignment Example I/O Clock Frequency Combinations Using M1025-11-155.5200 or M1026-11-155.5200 Input Reference Clock MHz PLL Ratio Pin Selectable devices M1025-11-155.5200 and M1026-11-155.5200 . See “Ordering Information” on pg. M1026 M/R Divider LUT Total MR_SEL3:0 M Div R Div PLL Ratio Fin for 155.52MHz VCSO MHz Phase Det. Freq. for 155.52MHz VCSO MHz 0000 4 1 0 1 16 4 0 1 0 64 16 0 1 256 64 0100 2 1 0101 8 4 0 1 0 32 16 0 1 128 64 1000 1 1001 4 1 0 1 0 16 1 0 1 64 1 0 Test Mode1 N/A 1 0 1 4 1 0 4 16 1 16 64 Table 4 M1026 M/R Divider LUT Note 1 Factory test mode do not use. M1025/26 Datasheet Rev 3 of 14 Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400 Integrated Circuit Systems, Inc. General Guidelines for M and R Divider Selection General guidelines for M/R divider selection see following pages for more detail : • A lower phase detector frequency should be used for loop timing applications to assure PLL tracking, especially during GR-253 jitter tolerance testing. The recommended maximum phase detector frequency for loop timing mode is 19.44MHz. The LOL pin should not be used during loop timing mode. • When LOL is to be used for system health monitoring, the phase detector frequency should be 5MHz or greater. Low phase detector frequencies make LOL overly sensitive, and higher phase detector frequencies make LOL less sensitive. • The preceding guideline also applies when using the AutoSwitch Mode, since AutoSwitch uses the LOL output for clock fault detection. P Divider Look-Up Table LUT The P_SEL1 and P_SEL0 pins select the post-PLL divider value P. The output frequency of the SAW can be divided by 1 or 2 or the output can be TriStated as specified in Table P_SEL1:0 00 01 10 11 the M1026-11-155.5200. “Ordering Information”, pg. Due to the narrow tuning range of the VCSO +200ppm , appropriate selection of all of the following are required for the PLL be able to lock VCSO center frequency, input frequency, and divider selections. Post-PLL Divider The M1025/26 features a post-PLL P divider. By using the P Divider, the device’s output frequency Fout can be the VCSO center frequency Fvcso or 1/2 Fvcso. The P_SEL pin selects the value for the P divider logic 1 sets P to 2, logic 0 sets P to See Table 5 on pg. When the P divider is included, the complete relation- ship for the output frequency Fout is defined as: Fout = --F----v---c---s---o---- = Fin x ------M----------- Due to the narrow tuning range of the VCSO +200ppm , appropriate selection of all of the following are required for the PLL be able to lock VCSO center frequency, input frequency, and divider selections. M1025/26 Datasheet Rev 5 of 14 Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400 Integrated Circuit Systems, Inc. TriState The TriState feature puts the LVPECL output driver into a high impedance state, effectively disconnecting the driver from the FOUT and nFOUT pins of the device. A logic 0 is then present on the clock net. The impedance of the clock net is then set to by the external circuit resistors. This is in distinction to a CMOS output in TriState, in which case the net goes to a high impedance and the logic value floats. The impedance level of the LVPECL TriState allows manufacturing In-circuit Test to drive the clock net with an external generator to validate the integrity of clock net and the clock load. Any unused output single-ended or differential should be left unconnected floating in system application. This minimizes output switching current and therefore minimizes noise modulation of the VCSO. Loss of Lock Indicator LOL Output Pin Under normal device operation, when the PLL is locked, the LOL Phase Detector drives LOL to logic Under circumstances when the VCSO cannot lock to the input as measured by a greater than 4 ns discrepancy between the feedback and reference clock rising edges at the LOL Phase Detector the LOL output goes to logic The LOL pin will return back to logic 0 when the phase detector error is less than 2 ns. The loss of lock indicator is a low current LVCMOS output. M1025/26 VCSO BASED CLOCK PLL WITH AUTOSWITCH Guidelines Using LOL As described, the LOL pin indicates when the PLL is out-of-lock with the input reference. The LOL condition is also used by the AutoSwitch circuit to detect a lost reference, as described in following sections. LOL is also used by the Hitless Switching and Phase Build-out functions optional device features . To ensure reliable operation of LOL and guard against false out-of-lock indications, the following conditions should be met: • The phase detector frequency should be no less than 5MHz, and preferably it should be 10MHz or greater. Phase detector frequency is defined by Fin / R. A higher phase detector frequency will result in lower phase error and less chance of false triggering the LOL phase detector. Refer to Tables 3 and 4 on pg. 3 for phase detector frequency when using the M1025-11-155.5200 or the M1026-11-155.5200. • The input reference should have an intrinsic jitter of less than 1 ns pk-pk. If reference jitter is greater than 1 ns pk-pk, the LOL circuit might falsely trigger. Due to this limitation, the LOL circuit should not be used in loop timing mode, nor should it be used with a noisy reference clock. Likewise, the AutoSwitch, Hitless Switching, or Phase Build-out features should not be used in loop timing mode or with a noisy reference clock, since these features depend on LOL. Reference Acknowledgement REF_ACK Output The REF_ACK reference acknowledgement pin outputs the value of the reference clock input that is routed to the phase detector. Logic 1 indicates input pair 1 nDIF_REF1, DIF_REF1 logic 0 indicates input pair 0 nDIF_REF0, DIF_REF0 . The REF_ACK indicator is an LVCMOS output. M1025/26 Datasheet Rev 6 of 14 Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400 Integrated Circuit Systems, Inc. M1025/26 VCSO BASED CLOCK PLL WITH AUTOSWITCH AutoSwitch AUTO Reference Clock Reselection This device offers an automatic reference clock reselection feature for switching input reference clocks upon a reference clock failure. With the AUTO input pin set to high and the LOL output low, the device is placed into automatic reselection AutoSwitch mode. Once in AutoSwitch mode, when LOL then goes high due to a reference clock fault , the input clock reference is automatically reselected internally, as indicated by the state change of the REF_ACK output. Automatic clock reselection is made only once it is non-revertive . Re-arming of automatic mode requires placing the device into manual selection Manual Select mode AUTO pin low before returning to AutoSwitch mode AUTO pin high . Using the AutoSwitch Feature The M1025/26 is available with a Hitless Switching feature that is enabled during device manufacturing. In addition, a Phase Build-out feature is also offered. These features are offered as device options and are specified by device order code. Refer to “Ordering Information” on pg. The Hitless Switching feature with or without Phase Build-out is designed for applications where switching occurs between two stable system reference clocks. It should not be used in loop timing applications, or when reference clock jitter is greater than 1 ns pk-pk. Hitless Switching is triggered by the LOL circuit, which is activated by a 4 ns phase transient. This magnitude of phase transient can generated by the CDR Clock & Data Recovery unit in loop timing mode, especially during a system jitter tolerance test. It can also be generated by some types of Stratum clock DPLLs digital PLL , especially those that do not include a post de-jitter APLL analog PLL . When the Hitless Switching feature is enabled, it is always triggered by LOL, whether in AutoSwitch mode AUTO pin high or Select mode AUTO pin low . For example, in Manual mode, the Hitless Switching feature operates when LOL goes high even if there is no reselection of the input mux. This enables the use of an upstream clock mux such as on the host card , while still providing MTIE compliance when readjusting to the resultant phase change. When the M1025/26 is operating in wide bandwidth mode NBW=0 , the optional Hitless Switching function puts the device into narrow bandwidth mode when activated. This allows the PLL to lock the new input clock phase gradually. With proper configuration of the external loop filter, the output clock complies with MTIE and TDEV specifications for GR-253 SONET and ITU G.813 SDH during input reference clock changes. The optional proprietary Phase Build-out PBO function enables the PLL to absorb most of the phase change of the input clock. The PBO function selects a new VCSO clock edge for the PLL Phase Detector feedback clock, selecting the edge closest in phase to the new input clock phase. This reduces re-lock time, the generation of wander, and extra output clock cycles. The Hitless Switching and Phase Build-out functions are triggered by the LOL circuit. For proper operation, a low phase detector frequency must be avoided. See “Guidelines Using LOL” on pg. 6 for information regarding the phase detector frequency. HS/PBO Triggers The HS function or the combined HS/PBO function is armed after the device locks to the input clock reference. Once armed, HS is triggered by the occurance of a Loss of Lock condition. This would typically occur as a consequence of a clock reference failure, a clock failure upstream to the M1025/26, or a M1025/26 clock reference mux reselection. When pin AUTO = 1 automatic reference reselection mode HS is used in conjunction with input reselection. When AUTO = 0 manual mode , HS will still occur upon an input phase transient, however the clock input is not reselected this enables hitless switching when using an external MUX for clock selection . HS/PBO Operation Once triggered, the following HS/PBO sequence occurs: The HS function disables the PLL Phase Detector and puts the device into NBW narrow bandwidth mode. The internal resistor Rin is changed to See the Narrow Bandwidth NBW Control Pin on pg. If included, the PBO function adds to builds out the phase in the clock feedback path in VCSO clock cycle increments to align the feedback clock with the new reference clock input phase. The PLL Phase Detector is enabled, allowing the PLL to re-lock. Once the PLL Phase Detector feedback and input clocks are locked to within 2 ns for eight consecutive cycles, a timer WBW timer for resuming wide bandwidth in 175 ns is started. Narrow Bandwidth NBW Control Pin A Narrow Loop Bandwidth control pin NBW pin is included to adjust the PLL loop bandwidth. In wide bandwidth mode NBW=0 , the internal resistor Rin is With the NBW pin asserted, the internal resistor Rin is changed to This lowers the loop bandwidth by a factor of about 21 approximately 2100 / 100 and lowers the damping factor by a factor of about the square root of 21 , assuming the same loop filter components. M1025/26 Datasheet Rev 8 of 14 Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400 Integrated Circuit Systems, Inc. External Loop Filter To provide stable PLL operation, the M1025/26 requires the use of an external loop filter. This is provided via the provided filter pins see Figure Due to the differential signal path design, the implementation requires two identical complementary RC filters as shown here. RLOOP CLOOP RPOST RLOOP CLOOP RPOST CPOST M1025/26 VCSO BASED CLOCK PLL WITH AUTOSWITCH PLL Simulator Tool Available A free PC software utility is available on the ICS website The M2000 Timing Modules PLL Simulator is a downloadable application that simulates PLL jitter and wander transfer characteristics. This enables the user to set appropriate external loop component values in a given application. For guidance on device or loop filter implementation, contact CMBU Commercial Business Unit Product Applications at 508 OP_IN nOP_IN OP_OUT nOP_OUT Figure 5 External Loop Filter nVC VC See Table 7, Example External Loop Filter Component Values, below. PLL Bandwidth is affected by loop filter component values, the “M” value, and the “PLL Loop Constants” listed in AC Characteristics on pg. The MR_SEL3:0 settings can be used to actively change PLL loop bandwidth in a given application. See “M and R Divider Look-Up Tables LUT ” on pg. Example External Loop Filter Component Values1 ORDERING INFORMATION Standard VCSO Output Frequencies MHz * Part Numbering Scheme Part Number: M102x- 1z - xxx.xxxx Frequency Input Divider Option 5 = Fin can equal Fvcso divided by 8, 2, or 1 6 = Fin can equal Fvcso divided by 4, 2, or 1 Output type 1 = LVPECL For CML or LVDS clock output, consult factory Hitless Switching / Phase Build-out Options 1 = none 2 = Hitless Switching 3 = Hitless Switching with Phase Build-out 4 = Phase Build-out without Hitless Switching Temperature “ - ” = 0 to +70 oC commercial I = - 40 to +85 oC industrial Table 12 Standard VCSO Output Frequencies MHz VCSO Frequency MHz See Table 12, right. Consult ICS for other frequencies. Figure 9 Part Numbering Scheme Note * Fout can equal Fvcso divided by 1 or 2 Consult ICS for the availability of other VCSO frequencies. Example Part Numbers VCSO Frequency MHz Temperature Order Part Number Examples commercial industrial commercial industrial M1025- 11- or M1026- 11- M1025- 11I155.5200 or M1026- 11I155.5200 M1025- 11- or M1026- 11- M1025- 11I156.2500 or M1026- 11I156.2500 Table 13 Example Part Numbers While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems ICS assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. M1025/26 Datasheet Rev 14 of 14 Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400

PDF Datasheet Preview

Integrated Circuit Systems, Inc.

M1025/26

VCSO BASED CLOCK PLL WITH AUTOSWITCH

The M1025/26 is a VCSO Voltage Controlled SAW Oscillator based clock jitter attenuator PLL designed for clock jitter attenuation and frequency translation. The device is ideal for generating the transmit reference clock for optical network systems supporting up to 2.5Gb data rates. It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop timing mode. The M1025/26 module includes a proprietary SAW surface acoustic wave delay line as part of the VCSO. This results in a high frequency, high-Q, low phase noise oscillator that assures low intrinsic output jitter.

PIN ASSIGNMENT 9 x 9 mm SMT
nDIF_REF1

DIF_REF1

REF_SEL
nDIF_REF0

DIF_REF0

MR_SEL3

MR_SEL2 MR_SEL0 MR_SEL1

LOL NBW VCC DNC
30 31

M1025
16 15

M1026

Top View

P_SEL0 P_SEL1 nFOUT FOUT GND REF_ACK AUTO VCC GND
nOP_IN

OP_OUT
nOP_OUT

OP_IN

Integrated SAW delay line low phase jitter of < 0.5ps rms, typical 12kHz to 20MHz

Output frequencies of to 175 MHz Specify VCSO output frequency at time of order

LVPECL clock output CML and LVDS options available

Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL

Loss of Lock LOL output pin Narrow Bandwidth control input NBW pin

AutoSwitch AUTO pin - automatic non-revertive reference clock reselection upon clock failure

Acknowledge pin REF_ACK pin indicates the actively selected reference input

Hitless Switching HS options with or without Phase Build-out PBO to enable SONET GR-253 /SDH G.813 MTIE and TDEV compliance during reselection

Pin-selectable feedback and reference divider ratios

Single 3.3V power supply

Small 9 x 9 mm SMT surface mount package

SIMPLIFIED BLOCK DIAGRAM

Figure 1 Pin Assignment

Example I/O Clock Frequency Combinations Using M1025-11-155.5200 or M1026-11-155.5200

Input Reference Clock MHz

PLL Ratio

Pin Selectable
devices M1025-11-155.5200 and M1026-11-155.5200 . See “Ordering Information” on pg.

M1026 M/R Divider LUT

Total MR_SEL3:0 M Div R Div PLL

Ratio

Fin for 155.52MHz VCSO MHz

Phase Det. Freq. for
155.52MHz VCSO MHz
0000 4 1
0 1 16 4
0 1 0 64 16
0 1 256 64
0100 2 1
0101 8 4
0 1 0 32 16
0 1 128 64
1000 1
1001 4
1 0 1 0 16
1 0 1 64
1 0 Test Mode1 N/A
1 0 1 4
1 0 4 16
1 16 64

Table 4 M1026 M/R Divider LUT

Note 1 Factory test mode do not use.

M1025/26 Datasheet Rev
3 of 14

Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400

Integrated Circuit Systems, Inc.

General Guidelines for M and R Divider Selection

General guidelines for M/R divider selection see following pages for more detail :
• A lower phase detector frequency should be used for
loop timing applications to assure PLL tracking, especially during GR-253 jitter tolerance testing. The recommended maximum phase detector frequency for loop timing mode is 19.44MHz. The LOL pin should not be used during loop timing mode.
• When LOL is to be used for system health monitoring,
the phase detector frequency should be 5MHz or greater. Low phase detector frequencies make LOL overly sensitive, and higher phase detector frequencies make LOL less sensitive.
• The preceding guideline also applies when using the

AutoSwitch Mode, since AutoSwitch uses the LOL output for clock fault detection.

P Divider Look-Up Table LUT

The P_SEL1 and P_SEL0 pins select the post-PLL divider value P. The output frequency of the SAW can be divided by 1 or 2 or the output can be TriStated as specified in Table

P_SEL1:0
00 01 10 11
the M1026-11-155.5200. “Ordering Information”, pg.

Due to the narrow tuning range of the VCSO +200ppm , appropriate selection of all of the following are required for the PLL be able to lock VCSO center frequency, input frequency, and divider selections.

Post-PLL Divider

The M1025/26 features a post-PLL P divider. By using the P Divider, the device’s output frequency Fout can be the VCSO center frequency Fvcso or 1/2 Fvcso.

The P_SEL pin selects the value for the P divider logic 1 sets P to 2, logic 0 sets P to See Table 5 on pg.

When the P divider is included, the complete relation-
ship for the output frequency Fout is defined as:

Fout = --F----v---c---s---o---- = Fin x ------M-----------

Due to the narrow tuning range of the VCSO
+200ppm , appropriate selection of all of the following
are required for the PLL be able to lock VCSO center
frequency, input frequency, and divider selections.

M1025/26 Datasheet Rev
5 of 14

Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400

Integrated Circuit Systems, Inc.

TriState

The TriState feature puts the LVPECL output driver into a high impedance state, effectively disconnecting the driver from the FOUT and nFOUT pins of the device. A logic 0 is then present on the clock net. The impedance of the clock net is then set to by the external circuit resistors. This is in distinction to a CMOS output in TriState, in which case the net goes to a high impedance and the logic value floats. The impedance level of the LVPECL TriState allows manufacturing In-circuit Test to drive the clock net with an external generator to validate the integrity of clock net and the clock load.

Any unused output single-ended or differential should be left unconnected floating in system application. This minimizes output switching current and therefore minimizes noise modulation of the VCSO.

Loss of Lock Indicator LOL Output Pin

Under normal device operation, when the PLL is locked, the LOL Phase Detector drives LOL to logic Under circumstances when the VCSO cannot lock to the input as measured by a greater than 4 ns discrepancy between the feedback and reference clock rising edges at the LOL Phase Detector the LOL output goes to logic The LOL pin will return back to logic 0 when the phase detector error is less than 2 ns. The loss of lock indicator is a low current LVCMOS output.

M1025/26

VCSO BASED CLOCK PLL WITH AUTOSWITCH

Guidelines Using LOL

As described, the LOL pin indicates when the PLL is out-of-lock with the input reference. The LOL condition is also used by the AutoSwitch circuit to detect a lost reference, as described in following sections. LOL is also used by the Hitless Switching and Phase Build-out functions optional device features .

To ensure reliable operation of LOL and guard against false out-of-lock indications, the following conditions should be met:
• The phase detector frequency should be no less than
5MHz, and preferably it should be 10MHz or greater. Phase detector frequency is defined by Fin / R. A higher phase detector frequency will result in lower phase error and less chance of false triggering the LOL phase detector. Refer to Tables 3 and 4 on pg. 3 for phase detector frequency when using the M1025-11-155.5200 or the M1026-11-155.5200.
• The input reference should have an intrinsic jitter of
less than 1 ns pk-pk. If reference jitter is greater than 1 ns pk-pk, the LOL circuit might falsely trigger. Due to this limitation, the LOL circuit should not be used in loop timing mode, nor should it be used with a noisy reference clock. Likewise, the AutoSwitch, Hitless Switching, or Phase Build-out features should not be used in loop timing mode or with a noisy reference clock, since these features depend on LOL.

Reference Acknowledgement REF_ACK Output

The REF_ACK reference acknowledgement pin outputs the value of the reference clock input that is routed to the phase detector. Logic 1 indicates input pair 1 nDIF_REF1, DIF_REF1 logic 0 indicates input pair 0 nDIF_REF0, DIF_REF0 . The REF_ACK indicator is an LVCMOS output.

M1025/26 Datasheet Rev
6 of 14

Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400

Integrated Circuit Systems, Inc.

M1025/26

VCSO BASED CLOCK PLL WITH AUTOSWITCH

AutoSwitch AUTO Reference Clock Reselection

This device offers an automatic reference clock reselection feature for switching input reference clocks upon a reference clock failure. With the AUTO input pin set to high and the LOL output low, the device is placed into automatic reselection AutoSwitch mode. Once in AutoSwitch mode, when LOL then goes high due to a reference clock fault , the input clock reference is automatically reselected internally, as indicated by the state change of the REF_ACK output. Automatic clock reselection is made only once it is non-revertive . Re-arming of automatic mode requires placing the device into manual selection Manual Select mode AUTO pin low before returning to AutoSwitch mode AUTO pin high .

Using the AutoSwitch Feature
The M1025/26 is available with a Hitless Switching feature that is enabled during device manufacturing. In addition, a Phase Build-out feature is also offered. These features are offered as device options and are specified by device order code. Refer to “Ordering Information” on pg.

The Hitless Switching feature with or without Phase Build-out is designed for applications where switching occurs between two stable system reference clocks. It should not be used in loop timing applications, or when reference clock jitter is greater than 1 ns pk-pk. Hitless Switching is triggered by the LOL circuit, which is activated by a 4 ns phase transient. This magnitude of phase transient can generated by the CDR Clock & Data Recovery unit in loop timing mode, especially during a system jitter tolerance test. It can also be generated by some types of Stratum clock DPLLs digital PLL , especially those that do not include a post de-jitter APLL analog PLL .

When the Hitless Switching feature is enabled, it is always triggered by LOL, whether in AutoSwitch mode AUTO pin high or Select mode AUTO pin low . For example, in Manual mode, the Hitless Switching feature operates when LOL goes high even if there is no reselection of the input mux. This enables the use of an upstream clock mux such as on the host card , while still providing MTIE compliance when readjusting to the resultant phase change.

When the M1025/26 is operating in wide bandwidth mode NBW=0 , the optional Hitless Switching function puts the device into narrow bandwidth mode when activated. This allows the PLL to lock the new input clock phase gradually. With proper configuration of the external loop filter, the output clock complies with MTIE and TDEV specifications for GR-253 SONET and ITU G.813 SDH during input reference clock changes.

The optional proprietary Phase Build-out PBO function enables the PLL to absorb most of the phase change of the input clock. The PBO function selects a new VCSO clock edge for the PLL Phase Detector feedback clock, selecting the edge closest in phase to the new input clock phase. This reduces re-lock time, the generation of wander, and extra output clock cycles.

The Hitless Switching and Phase Build-out functions are triggered by the LOL circuit. For proper operation, a low phase detector frequency must be avoided. See “Guidelines Using LOL” on pg. 6 for information regarding the phase detector frequency.

HS/PBO Triggers

The HS function or the combined HS/PBO function is armed after the device locks to the input clock reference. Once armed, HS is triggered by the occurance of a Loss of Lock condition. This would typically occur as a consequence of a clock reference failure, a clock failure upstream to the M1025/26, or a M1025/26 clock reference mux reselection.

When pin AUTO = 1 automatic reference reselection mode HS is used in conjunction with input reselection. When AUTO = 0 manual mode , HS will still occur upon an input phase transient, however the clock input is not reselected this enables hitless switching when using an external MUX for clock selection .

HS/PBO Operation Once triggered, the following HS/PBO sequence occurs:

The HS function disables the PLL Phase Detector and puts the device into NBW narrow bandwidth mode. The internal resistor Rin is changed to See the Narrow Bandwidth NBW Control Pin on pg.

If included, the PBO function adds to builds out the phase in the clock feedback path in VCSO clock cycle increments to align the feedback clock with the new reference clock input phase.

The PLL Phase Detector is enabled, allowing the PLL to re-lock.

Once the PLL Phase Detector feedback and input clocks are locked to within 2 ns for eight consecutive cycles, a timer WBW timer for resuming wide bandwidth in 175 ns is started.

Narrow Bandwidth NBW Control Pin

A Narrow Loop Bandwidth control pin NBW pin is included to adjust the PLL loop bandwidth. In wide bandwidth mode NBW=0 , the internal resistor Rin is With the NBW pin asserted, the internal resistor Rin is changed to This lowers the loop bandwidth by a factor of about 21 approximately 2100 / 100 and lowers the damping factor by a factor of about the square root of 21 , assuming the same loop filter components.

M1025/26 Datasheet Rev
8 of 14

Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400

Integrated Circuit Systems, Inc.

External Loop Filter

To provide stable PLL operation, the M1025/26 requires the use of an external loop filter. This is provided via the provided filter pins see Figure

Due to the differential signal path design, the implementation requires two identical complementary RC filters as shown here.

RLOOP CLOOP

RPOST

RLOOP CLOOP

RPOST

CPOST

M1025/26

VCSO BASED CLOCK PLL WITH AUTOSWITCH

PLL Simulator Tool Available

A free PC software utility is available on the ICS website The M2000 Timing Modules PLL Simulator is a downloadable application that simulates PLL jitter and wander transfer characteristics. This enables the user to set appropriate external loop component values in a given application.

For guidance on device or loop filter implementation, contact CMBU Commercial Business Unit Product Applications at 508

OP_IN nOP_IN

OP_OUT nOP_OUT

Figure 5 External Loop Filter
nVC VC

See Table 7, Example External Loop Filter Component Values, below.

PLL Bandwidth is affected by loop filter component values, the “M” value, and the “PLL Loop Constants” listed in AC Characteristics on pg.

The MR_SEL3:0 settings can be used to actively change PLL loop bandwidth in a given application. See “M and R Divider Look-Up Tables LUT ” on pg.

Example External Loop Filter Component Values1
ORDERING INFORMATION

Standard VCSO Output Frequencies MHz *

Part Numbering Scheme

Part Number:

M102x- 1z - xxx.xxxx

Frequency Input Divider Option
5 = Fin can equal Fvcso divided by 8, 2, or 1 6 = Fin can equal Fvcso divided by 4, 2, or 1

Output type 1 = LVPECL For CML or LVDS clock output, consult factory

Hitless Switching / Phase Build-out Options 1 = none 2 = Hitless Switching 3 = Hitless Switching with Phase Build-out 4 = Phase Build-out without Hitless Switching

Temperature
“ - ” = 0 to +70 oC commercial I = - 40 to +85 oC industrial

Table 12 Standard VCSO Output Frequencies MHz

VCSO Frequency MHz See Table 12, right. Consult ICS for other frequencies.

Figure 9 Part Numbering Scheme

Note * Fout can equal Fvcso divided by 1 or 2

Consult ICS for the availability of other VCSO frequencies.

Example Part Numbers

VCSO Frequency MHz Temperature

Order Part Number Examples
commercial industrial commercial industrial

M1025- 11- or M1026- 11- M1025- 11I155.5200 or M1026- 11I155.5200 M1025- 11- or M1026- 11- M1025- 11I156.2500 or M1026- 11I156.2500

Table 13 Example Part Numbers

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems ICS assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.

M1025/26 Datasheet Rev
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Integrated Circuit Systems, Inc. ● Networking & Communications ● ● tel 508 852-5400

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived M1026-13-155.5200 Datasheet file may be downloaded here without warranties.

Datasheet ID: M1026-13-155.5200 637412