CV125PAG

CV125PAG Datasheet

IDTCV125 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

Part	Datasheet
CV125PAG	CV125PAG (pdf)

Related Parts	Information
CV125PAG8	CV125PAG8

PDF Datasheet Preview
IDTCV125 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR IDTCV125 FEATURES: • Power management control suitable for notebook applications • One high precision PLL for CPU, SSC and N programming • One high precision PLL for SRC/PCI, supports 100MHz output frequency, SSC and N programming • One high precision PLL for LVDS. Supports 100/96MHz output frequency, SSC programming • One high precision PLL for 96MHz/48MHz • Band-gap circuit for differential outputs • Support spread spectrum modulation, down spread and others • Support SMBus block read/write, index read/write • Selectable output strength for REF • Allows for CPU frequency to change to a slower frequency to conserve power when an application is less executionintensive • Smooth transition for N programming • Available in TSSOP package KEY SPECIFICATION: • CPU/SRC CLK cycle to cycle jitter < 85ps • PCI CLK cycle to cycle jitter < 250ps • Static PLL frequency divide error < 114 ppm • Static PLL frequency divide error for 48MHz < 5 ppm DESCRIPTION: IDTCV125 is a 56 pin clock device, incorporating both Intel CK410M and CKSSCD requirements, for Intel advance P4 processors. The CPU output buffer is designed to support up to 400MHz processor. This chip has four PLLs inside for CPU, SRC/PCI, LVDS, and 48MHz/DOT96 IO clocks. This device also implements Band-gap referenced IREF to reduce the impact of VDD variation on differential outputs, which can provide more robust system performance. Static PLL frequency divide error can be as low as 36 ppm, worse case 114 ppm, providing high accuracy output clock. Each CPU/SRC/LVDS has its own Spread Spectrum selection. OUTPUTS: • 20.7V current differential CPU CLK pair • 60.7V current differential SRC CLK pair • One CPU_ITP/SRC selectable CLK pair • 6PCI, 2 free running, 33.3MHz • 196MHz, 148MHz • 1REF • One 100/96 MHz differential LVDS FUNCTIONAL BLOCK DIAGRAM X1 X2 SDATA SCLK XTAL Osc Amp SM Bus Controller VTT_PWRGD#/PD SEL100/96# FSA.B.C PCI_STOP# CPU_STOP# SEL 100/96MHz Control Logic PLL1 SSC N Programmable PLL2 SSC PLL3 SSC N Programmable CPU CLK Output Buffer Stop Logic IREF LVDS CLK Output Buffer Stop Logic IREF ITP_EN SRC CLK Output Buffer Stop Logic IREF PLL4 48MHz/96MHz Output BUffer The IDT logo is a registered trademark of Integrated Device Technology, Inc. ORDERING INFORMATION IDTCV XXX Device Type Package X Grade COMMERCIAL TEMPERATURE RANGE Blank Commercial Temperature Range 0°C to +70°C PA Thin Small Shrink Outline Package PAG TSSOP - Green 125 Programmable FlexPC Clock for P4 Processor CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support:

PDF Datasheet Preview

IDTCV125 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

COMMERCIAL TEMPERATURE RANGE

PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

IDTCV125

FEATURES:
• Power management control suitable for notebook applications
• One high precision PLL for CPU, SSC and N programming
• One high precision PLL for SRC/PCI, supports 100MHz output
frequency, SSC and N programming
• One high precision PLL for LVDS. Supports 100/96MHz output
frequency, SSC programming
• One high precision PLL for 96MHz/48MHz
• Band-gap circuit for differential outputs
• Support spread spectrum modulation, down spread and
others
• Support SMBus block read/write, index read/write
• Selectable output strength for REF
• Allows for CPU frequency to change to a slower frequency to
conserve power when an application is less executionintensive
• Smooth transition for N programming
• Available in TSSOP package

KEY SPECIFICATION:
• CPU/SRC CLK cycle to cycle jitter < 85ps
• PCI CLK cycle to cycle jitter < 250ps
• Static PLL frequency divide error < 114 ppm
• Static PLL frequency divide error for 48MHz < 5 ppm

DESCRIPTION:

IDTCV125 is a 56 pin clock device, incorporating both Intel CK410M and CKSSCD requirements, for Intel advance P4 processors. The CPU output buffer is designed to support up to 400MHz processor. This chip has four PLLs inside for CPU, SRC/PCI, LVDS, and 48MHz/DOT96 IO clocks. This device also implements Band-gap referenced IREF to reduce the impact of VDD variation on differential outputs, which can provide more robust system performance.

Static PLL frequency divide error can be as low as 36 ppm, worse case 114 ppm, providing high accuracy output clock. Each CPU/SRC/LVDS has its own Spread Spectrum selection.

OUTPUTS:
• 2*0.7V current differential CPU CLK pair
• 6*0.7V current differential SRC CLK pair
• One CPU_ITP/SRC selectable CLK pair
• 6*PCI, 2 free running, 33.3MHz
• 1*96MHz, 1*48MHz
• 1*REF
• One 100/96 MHz differential LVDS

FUNCTIONAL BLOCK DIAGRAM

X1 X2

SDATA SCLK

XTAL Osc Amp

SM Bus Controller

VTT_PWRGD#/PD SEL100/96# FSA.B.C PCI_STOP# CPU_STOP#

SEL 100/96MHz

Control Logic

PLL1 SSC N Programmable

PLL2 SSC

PLL3 SSC N Programmable

CPU CLK Output Buffer

Stop Logic

IREF

LVDS CLK Output Buffer

Stop Logic

IREF

ITP_EN

SRC CLK Output Buffer

Stop Logic

IREF

PLL4
48MHz/96MHz Output BUffer

The IDT logo is a registered trademark of Integrated Device Technology, Inc.
ORDERING INFORMATION

IDTCV XXX

Device Type Package

X Grade

COMMERCIAL TEMPERATURE RANGE

Blank Commercial Temperature Range 0°C to +70°C

PA Thin Small Shrink Outline Package PAG TSSOP - Green
125 Programmable FlexPC Clock for P4 Processor

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775
for Tech Support:

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CV125PAG Datasheet file may be downloaded here without warranties.

Datasheet ID: CV125PAG 637404