IDT85304-01PGGI

IDT85304-01PGGI Datasheet

IDT85304-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL

Part	Datasheet
IDT85304-01PGGI	IDT85304-01PGGI (pdf)

Related Parts	Information
IDT85304-01PGG	IDT85304-01PGG
IDT85304-01PGG8	IDT85304-01PGG8
IDT85304-01PGGI8	IDT85304-01PGGI8

PDF Datasheet Preview
IDT85304-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER IDT85304-01 FEATURES: • Five differential 3.3V LVPECL outputs • Selectable differential CLK, xCLK, or LVPECL clock inputs • CLK, xCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, and HCSL • PCLK, xPCLK supports the following input types LVPECL, CML, and SSTL • Maximum output frequency 650MHz • Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on xCLK input • Output skew 35ps max. • Part-to-part skew as low as 150ps • Propagation delay 2.1ns max. • 3.3V operating supply • Available in TSSOP package DESCRIPTION: The IDT85304-01 is a low skew, high performance 1-to-5 differential-to3.3V LVPECL clock generator-divider. It has two selectable clock inputs. The CLK/ xCLK pair can accept most standard differential input levels. The PCLK/ xPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the IDT8530401 ideal for those applications that demand well-defined performance and repeatability. FUNCTIONAL BLOCK DIAGRAM CLK_EN xCLK PCLK xPCLK CLK_SEL The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL c 2006 Integrated Device Technology, Inc. TEMPERATURE 1 RANGES Q0 xQ0 Q1 xQ1 Q2 xQ2 Q3 xQ3 Q4 xQ4 FEBRUARY 2009 DSC 6174/8 IDT85304-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PIN CONFIGURATION CLK_EN xPCLK PCLK xCLK CLK_SEL TSSOP TOP VIEW COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS 1 Symbol VDD VI VO Description Power Supply Voltage Input Voltage Output Voltage Package Thermal Impedance 0 lfpm Unit to VDD+0.5 V to VDD+0.5 V ORDERING INFORMATION Device Type Package Process COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Blank I Commercial 0°C to +70°C Industrial -40°C to +85°C PG PGG Thin Shrink Small Outline Package TSSOP - Green 85304-01 Low Skew, 1-to-5 Differential-to-3.3V LVPECL Fanout Buffer CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support:

PDF Datasheet Preview

IDT85304-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER

IDT85304-01

FEATURES:
• Five differential 3.3V LVPECL outputs
• Selectable differential CLK, xCLK, or LVPECL clock inputs
• CLK, xCLK pair can accept the following differential input levels:

LVDS, LVPECL, LVHSTL, SSTL, and HCSL
• PCLK, xPCLK supports the following input types LVPECL, CML,
and SSTL
• Maximum output frequency 650MHz
• Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on xCLK input
• Output skew 35ps max.
• Part-to-part skew as low as 150ps
• Propagation delay 2.1ns max.
• 3.3V operating supply
• Available in TSSOP package

DESCRIPTION:

The IDT85304-01 is a low skew, high performance 1-to-5 differential-to3.3V LVPECL clock generator-divider. It has two selectable clock inputs. The CLK/ xCLK pair can accept most standard differential input levels. The PCLK/ xPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.

Guaranteed output and part-to-part skew characteristics make the IDT8530401 ideal for those applications that demand well-defined performance and repeatability.

FUNCTIONAL BLOCK DIAGRAM

CLK_EN
xCLK

PCLK
xPCLK

CLK_SEL

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL
c 2006 Integrated Device Technology, Inc.

TEMPERATURE 1

RANGES

Q0 xQ0 Q1 xQ1 Q2 xQ2 Q3 xQ3 Q4 xQ4

FEBRUARY 2009

DSC 6174/8

IDT85304-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL

PIN CONFIGURATION

CLK_EN
xPCLK

PCLK
xCLK

CLK_SEL

TSSOP TOP VIEW

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS 1

Symbol VDD VI VO

Description Power Supply Voltage Input Voltage Output Voltage Package Thermal Impedance 0 lfpm

Unit
to VDD+0.5 V
to VDD+0.5 V
ORDERING INFORMATION

Device Type Package Process

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

Blank I

Commercial 0°C to +70°C Industrial -40°C to +85°C

PG PGG

Thin Shrink Small Outline Package TSSOP - Green
85304-01 Low Skew, 1-to-5 Differential-to-3.3V LVPECL Fanout Buffer

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775
for Tech Support:

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT85304-01PGGI Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT85304-01PGGI 637396