82V3002APVG8

82V3002APVG8 Datasheet

IDT82V3002A

Part	Datasheet
82V3002APVG8	82V3002APVG8 (pdf)

Related Parts	Information
82V3002APVG	82V3002APVG

PDF Datasheet Preview
WAN PLL WITH DUAL REFERENCE INPUTS IDT82V3002A • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ITU-T G.813 Option 1 clocks for 2048 kbit/s interfaces • Supports ITU-T G.812 Type IV clocks for 1544 kbit/s interface and 2048 kbit/s interfaces • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface • Selectable input reference signal 8 kHz, MHz or MHz • Accepts reference inputs from two independent sources • Provides eight types of clock signals C1.5o, C3o, C2o, C4o, C6o, C8o, C16o and C32o • Provides six types of 8 kHz framing pulses F0o, F8o, F16o, F32o, RSP and TSP • Holdover frequency accuracy of ppm • Phase slope of 5 ns/125 µs • Attenuates wander from Hz • Fast Lock mode • Provides Time Interval Error TIE correction • MTIE of 600 ns • JTAG boundary scan • Holdover status indication • Freerun status indication • Normal status indication • Lock status indication • Input primary reference quality indication • V operation with 5 V tolerant I/O • Package available 56-pin SSOP Green option available The IDT82V3002A is a WAN PLL with dual reference inputs. It contains a Digital Phase-Locked Loop DPLL , which generates ST-BUS clocks and framing signals that are phase locked to a MHz, MHz or 8 kHz input reference. The IDT82V3002A provides eight types of clock signals C1.5o, C3o, C6o, C2o, C4o, C8o, C16o, C32o and six types of framing signals F0o, F8o, F16o, F32o, RSP, TSP for the multitrunk T1 and E1 primary rate transmission links. The IDT82V3002A is compliant with AT&T TR62411, Telcordia GR1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4, ETSI ETS 300 011, ITU-T G.813 Option 1 for 2048 kbit/s interface, and ITU-T G.812 Type IV clocks for 1544 kbit/s interface and 2048 kbit/s interface. It meets the jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture range, phase change slope, holdover frequency accuracy and MTIE Maximum Time Interval Error requirements for these specifications. The IDT82V3002A can be used in synchronization and timing control for T1 and E1 systems, or used as ST-BUS clock and frame pulse sources. It can also be used in access switch, access routers, ATM edge switches, wireless base station controllers, or IADs Integrated Access Devices , PBXs and line cards. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Integrated Device Technology, Inc. October 15, 2008 DSC-6243/4 IDT82V3002A FUNCTIONAL BLOCK DIAGRAM WAN PLL WITH DUAL REFERENCE INPUT Fref0 Fref1 IN_sel FLOCK MON_out TDI TMS TRST OSCi OSCo TCLR VDDD VSS VDDD VSS VDDD VSS VDDA VSS VDDA VSS Reference Input Switch Reference Input Monitor Invalid Input Signal Detection TIE Control Block Virtual Reference DPLL Feedback Signal C32o C16o C8o C4o C2o C3o C1.5o C6o F0o F8o F16o F32o RSP TSP LOCK JTAG State Control Circuit Frequency Select Circuit 7 ORDERING INFORMATION 29 Table Of Contents October 15, 2008 LIST OF FIGURES Figure - 1 Block Diagram 2 Figure - 2 IDT82V3002A SSOP56 Package Pin 6 Figure - 3 State Control 10 Figure - 4 State Control 11 Figure - 5 TIE Control Circuit Diagram 13 Figure - 6 Reference Switch with TIE Control Block 13 Figure - 7 Reference Switch with TIE Control Block 14 Figure - 8 DPLL Block Diagram 15 Figure - 9 Clock Oscillator Circuit 16 Figure - 10 Power-Up Reset 16 Figure - 11 IDT82V3002A Power Decoupling Scheme 17 Figure - 12 Input to Output Timing Normal 26 Figure - 13 Output Timing 27 Figure - 14 Output Timing 28 Figure - 15 Input Control Setup and Hold Timing 28 List of Figures October 15, 2008 LIST OF TABLES Table - 1 Pin Description 7 Table - 2 Operating Modes and Table - 3 Input Reference Frequency Selection 12 Table - 4 Reference Input Switch 12 Table - 5 Absolute Maximum 20 Table - 6 Recommended DC Operating Conditions 20 Table - 7 DC Electrical Characteristics 20 Table - 8 Performance** 21 Table - 9 Intrinsic Jitter 21 Table - 10 C1.5o MHz Intrinsic Jitter 22 Table - 11 C2o MHz Intrinsic Jitter 22 Table - 12 8 kHz Input to 8 kHz Output Jitter Transfer 22 Table - 13 MHz Input to MHz Output Jitter 22 Table - 14 MHz Input to MHz Output Jitter 23 Table - 15 8 kHz Input Jitter Tolerance 23 Table - 16 MHz Input Jitter Tolerance 23 Table - 17 MHz Input Jitter Tolerance 24 Table - 18 Timing Parameter Measurement Voltage Levels 25 Table - 19 Input / Output 25 List of Tables October 15, 2008 IDT82V3002A IDT82V3002A PIN CONFIGURATION WAN PLL WITH DUAL REFERENCE INPUT MODE_sel0 MODE_sel1 TCLR Fref0 Fref1 MON_out F_sel0 F_sel1 IN_sel VDDD C1.5o VDDD C16o C32o VDDD TIE_en HOLDOVER FREERUN OSCi OSCo VDDA NORMAL FLOCK LOCK F32o F16o VDDA ORDERING INFORMATION WAN PLL WITH DUAL REFERENCE INPUT Device Type XX Package Process/ Temperature Range Blank Industrial -40 °C to +85 °C PV PVG Shrink Small Outline Package SSOP, PV56 Green - Shrink Small Outline Package SSOP, PVG56 82V3002A WAN PLL with Dual Reference Inputs DATASHEET DOCUMENT HISTORY 10/22/2003 pgs. 7, 24, 25 11/18/2004 pgs. 1, 28 05/24/2006 pgs. 6, 7, 17 10/15/2008 pgs. 29 removed "IDT" from the orderable part number. CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 1-800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support 408-360-1552 The IDT logo is a registered trademark of Integrated Device Technology, Inc.

PDF Datasheet Preview

WAN PLL WITH DUAL REFERENCE INPUTS

IDT82V3002A
• Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces
• Supports ITU-T G.813 Option 1 clocks for 2048 kbit/s interfaces
• Supports ITU-T G.812 Type IV clocks for 1544 kbit/s interface and 2048 kbit/s interfaces
• Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface
• Selectable input reference signal 8 kHz, MHz or MHz
• Accepts reference inputs from two independent sources
• Provides eight types of clock signals C1.5o, C3o, C2o, C4o,

C6o, C8o, C16o and C32o
• Provides six types of 8 kHz framing pulses F0o, F8o, F16o,

F32o, RSP and TSP
• Holdover frequency accuracy of ppm
• Phase slope of 5 ns/125 µs
• Attenuates wander from Hz
• Fast Lock mode
• Provides Time Interval Error TIE correction
• MTIE of 600 ns
• JTAG boundary scan
• Holdover status indication
• Freerun status indication
• Normal status indication
• Lock status indication
• Input primary reference quality indication
• V operation with 5 V tolerant I/O
• Package available 56-pin SSOP Green option available

The IDT82V3002A is a WAN PLL with dual reference inputs. It contains a Digital Phase-Locked Loop DPLL , which generates ST-BUS clocks and framing signals that are phase locked to a MHz, MHz or 8 kHz input reference.

The IDT82V3002A provides eight types of clock signals C1.5o, C3o, C6o, C2o, C4o, C8o, C16o, C32o and six types of framing signals F0o, F8o, F16o, F32o, RSP, TSP for the multitrunk T1 and E1 primary rate transmission links.

The IDT82V3002A is compliant with AT&T TR62411, Telcordia GR1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4, ETSI ETS 300 011, ITU-T G.813 Option 1 for 2048 kbit/s interface, and ITU-T G.812

Type IV clocks for 1544 kbit/s interface and 2048 kbit/s interface. It meets the jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture range, phase change slope, holdover frequency accuracy and MTIE Maximum Time Interval Error requirements for these specifications.

The IDT82V3002A can be used in synchronization and timing control for T1 and E1 systems, or used as ST-BUS clock and frame pulse sources. It can also be used in access switch, access routers, ATM edge switches, wireless base station controllers, or IADs Integrated Access Devices , PBXs and line cards.

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.

Integrated Device Technology, Inc.

October 15, 2008

DSC-6243/4

IDT82V3002A

FUNCTIONAL BLOCK DIAGRAM

WAN PLL WITH DUAL REFERENCE INPUT

Fref0 Fref1 IN_sel FLOCK MON_out

TDI TMS TRST

OSCi

OSCo

TCLR VDDD VSS VDDD VSS VDDD VSS VDDA VSS VDDA VSS

Reference Input Switch

Reference Input Monitor

Invalid Input Signal

Detection

TIE Control Block

Virtual Reference

DPLL

Feedback Signal

C32o C16o C8o C4o C2o C3o C1.5o C6o F0o F8o F16o F32o RSP TSP

LOCK

JTAG

State Control Circuit

Frequency Select Circuit
7 ORDERING INFORMATION 29

Table Of Contents

October 15, 2008

LIST OF FIGURES

Figure - 1 Block Diagram 2 Figure - 2 IDT82V3002A SSOP56 Package Pin 6 Figure - 3 State Control 10 Figure - 4 State Control 11 Figure - 5 TIE Control Circuit Diagram 13 Figure - 6 Reference Switch with TIE Control Block 13 Figure - 7 Reference Switch with TIE Control Block 14 Figure - 8 DPLL Block Diagram 15 Figure - 9 Clock Oscillator Circuit 16 Figure - 10 Power-Up Reset 16 Figure - 11 IDT82V3002A Power Decoupling Scheme 17 Figure - 12 Input to Output Timing Normal 26 Figure - 13 Output Timing 27 Figure - 14 Output Timing 28 Figure - 15 Input Control Setup and Hold Timing 28

List of Figures

October 15, 2008

LIST OF TABLES

Table - 1 Pin Description 7 Table - 2 Operating Modes and Table - 3 Input Reference Frequency Selection 12 Table - 4 Reference Input Switch 12 Table - 5 Absolute Maximum 20 Table - 6 Recommended DC Operating Conditions** 20 Table - 7 DC Electrical Characteristics** 20 Table - 8 Performance** 21 Table - 9 Intrinsic Jitter 21 Table - 10 C1.5o MHz Intrinsic Jitter 22 Table - 11 C2o MHz Intrinsic Jitter 22 Table - 12 8 kHz Input to 8 kHz Output Jitter Transfer 22 Table - 13 MHz Input to MHz Output Jitter 22 Table - 14 MHz Input to MHz Output Jitter 23 Table - 15 8 kHz Input Jitter Tolerance 23 Table - 16 MHz Input Jitter Tolerance 23 Table - 17 MHz Input Jitter Tolerance 24 Table - 18 Timing Parameter Measurement Voltage Levels 25 Table - 19 Input / Output 25

List of Tables

October 15, 2008

IDT82V3002A

IDT82V3002A PIN CONFIGURATION

WAN PLL WITH DUAL REFERENCE INPUT

MODE_sel0

MODE_sel1

TCLR

Fref0

Fref1

MON_out

F_sel0

F_sel1

IN_sel

VDDD

C1.5o

VDDD

C16o

C32o

VDDD

TIE_en

HOLDOVER

FREERUN

OSCi

OSCo

VDDA

NORMAL

FLOCK

LOCK

F32o

F16o

VDDA
ORDERING INFORMATION

WAN PLL WITH DUAL REFERENCE INPUT

Device Type

XX Package

Process/ Temperature

Range

Blank

Industrial -40 °C to +85 °C

PV PVG

Shrink Small Outline Package SSOP, PV56 Green - Shrink Small Outline Package SSOP, PVG56
82V3002A WAN PLL with Dual Reference Inputs

DATASHEET DOCUMENT HISTORY
10/22/2003 pgs. 7, 24, 25
11/18/2004 pgs. 1, 28
05/24/2006 pgs. 6, 7, 17
10/15/2008 pgs. 29 removed "IDT" from the orderable part number.

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 1-800-345-7015 or 408-284-8200 fax 408-284-2775
for Tech Support 408-360-1552

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 82V3002APVG8 Datasheet file may be downloaded here without warranties.

Datasheet ID: 82V3002APVG8 637394