IDT82P2808BBG

IDT82P2808BBG Datasheet

Line Interface Unit IDT82P2808

Part	Datasheet
IDT82P2808BBG	IDT82P2808BBG (pdf)

Related Parts	Information
IDT82P2808BB	IDT82P2808BB

PDF Datasheet Preview
8 +1 Channel High-Density T1/E1/J1 Line Interface Unit IDT82P2808 Version 2 February 6, 2009 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone 1-800-345-7015 or 408-284-8200• TWX 910-338-2070 • FAX 408-284-2775 Printed in U.S.A. 2009 Integrated Device Technology, Inc. DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc. LIFE SUPPORT POLICY Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT. Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Table of Contents TABLE OF CONTENTS 3 LIST OF TABLES 7 LIST OF FIGURES 8 FEATURES 10 BLOCK DIAGRAM 12 1 PIN ASSIGNMENT 13 2 PIN DESCRIPTION 14 3 FUNCTIONAL DESCRIPTION 24 T1 / E1 / J1 MODE SELECTION 24 RECEIVE PATH 24 Rx Termination 24 Receive Differential Mode 24 Receive Single Ended Mode 26 Equalizer 27 Line Monitor 27 Receive Sensitivity 27 Slicer 28 Rx Clock & Data Recovery 28 Decoder 28 Receive System Interface 28 Receiver Power Down 29 TRANSMIT PATH 29 Transmit System Interface 29 Tx Clock Recovery 30 Encoder 30 Waveform Shaper 30 Preset Waveform Template 30 User-Programmable Arbitrary Waveform 32 Line Driver 34 Transmit Over Current Protection 34 Tx Termination 34 Transmit Differential Mode 34 Transmit Single Ended Mode 35 Transmitter Power Down 36 Output High-Z on TTIP and TRING 36 JITTER ATTENUATOR RJA & TJA 37 Table of Contents February 6, 2009 IDT82P2808 8 +1 CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT DIAGNOSTIC FACILITIES 38 Bipolar Violation BPV / Code Violation CV Detection and BPV Insertion 38 Bipolar Violation BPV / Code Violation CV Detection 38 Bipolar Violation BPV Insertion 38 Excessive Zeroes EXZ Detection 38 Loss of Signal LOS Detection 39 Line LOS LLOS 39 System LOS SLOS 40 Transmit LOS TLOS 41 Alarm Indication Signal AIS Detection and Generation 42 Alarm Indication Signal AIS Detection 42 Alarm Indication Signal AIS Generation 42 PRBS, QRSS, ARB and IB Pattern Generation and Detection 43 Pattern Generation 43 Pattern Detection 44 Error Counter 45 Automatic Error Counter Updating 45 Manual Error Counter Updating 46 Receive /Transmit Multiplex Function RMF / TMF Indication 47 RMFn Indication 47 TMFn Indication 48 Loopback 49 Analog Loopback 49 Remote Loopback 50 Digital Loopback 51 Dual Loopback 52 Channel 0 Monitoring 54 G.772 Monitoring 54 Jitter Measurement JM 55 CLOCK INPUTS AND OUTPUTS 56 Free Running Clock Outputs on CLKT1/CLKE1 56 Clock Outputs on REFA/REFB 57 REFA/REFB in Clock Recovery Mode 57 Frequency Synthesizer for REFA Clock Output 57 Free Run Mode for REFA Clock Output 57 REFA/REFB Driven by External CLKA/CLKB Input 57 REFA and REFB in Loss of Signal LOS or Loss of Clock Condition 57 MCLK, Master Clock Input 61 XCLK, Internal Reference Clock Input 61 INTERRUPT SUMMARY 62 4 MISCELLANEOUS 64 RESET 64 Power-On Reset 65 Hardware Reset 65 Global Software Reset 65 Table of Contents February 6, 2009 IDT82P2808 8 +1 CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT Per-Channel Software Reset 65 MICROPROCESSOR INTERFACE 65 POWER UP 66 HITLESS PROTECTION SWITCHING HPS SUMMARY 66 5 PROGRAMMING INFORMATION 69 REGISTER MAP 69 Global Register 69 Per-Channel Register 70 REGISTER DESCRIPTION 73 Global Register 73 Per-Channel Register 81 6 JTAG 111 JTAG INSTRUCTION REGISTER IR 111 JTAG DATA REGISTER 111 Device Identification Register IDR 111 Bypass Register BYP 111 Boundary Scan Register BSR 111 TEST ACCESS PORT TAP CONTROLLER 111 ORDERING INFORMATION 144 Table of Contents February 6, 2009 List of Tables Table-1 Operation Mode Selection 24 Table-2 Impedance Matching Value in Receive Differential Mode 25 Table-3 Multiplex Pin Used in Receive System Interface 28 Table-4 Multiplex Pin Used in Transmit System Interface 30 Table-5 PULS[3:0] Setting in T1/J1 Mode 30 Table-6 PULS[3:0] Setting in E1 Mode 31 Table-7 Transmit Waveform Value for T1 0 ~ 133 ft 33 Table-8 Transmit Waveform Value for T1 133 ~ 266 ft 33 Table-9 Transmit Waveform Value for T1 266 ~ 399 ft 33 Table-10 Transmit Waveform Value for T1 399 ~ 533 ft 33 Table-11 Transmit Waveform Value for T1 533 ~ 655 ft 33 Table-12 Transmit Waveform Value for E1 75 ohm 33 Table-13 Transmit Waveform Value for E1 120 ohm 33 Table-14 Transmit Waveform Value for J1 0 ~ 655 ft 33 Table-15 Impedance Matching Value in Transmit Differential Mode 34 Table-16 EXZ Definition 38 Table-17 LLOS Criteria 39 Table-18 SLOS Criteria 40 Table-19 TLOS Detection Between Two Channels 41 Table-20 AIS Criteria 42 Table-21 RMFn Indication 47 Table-22 TMFn Indication 48 Table-23 Clock Output on CLKT1 56 Table-24 Clock Output on CLKE1 56 Table-25 Interrupt Summary 62 Table-26 After Reset Effect Summary 64 Table-27 Microprocessor Interface 65 List of Tables February 6, 2009 List of Figures Figure-1 Functional Block Diagram 12 Figure-2 416-Pin PBGA Top View 13 Figure-3 Switch between Impedance Matching Modes 24 Figure-4 Receive Differential Line Interface with Twisted Pair Cable with transformer 25 Figure-5 Receive Differential Line Interface with Coaxial Cable with transformer 25 Figure-6 Receive Differential Line Interface with Twisted Pair Cable transformer-less, non standard compliant 26 Figure-7 Receive Single Ended Line Interface with Coaxial Cable with transformer 26 Figure-8 Receive Single Ended Line Interface with Coaxial Cable transformer-less, non standard compliant 26 Figure-9 Receive Path Monitoring 27 Figure-10 Transmit Path Monitoring 27 Figure-11 DSX-1 Waveform Template 30 Figure-12 T1 Waveform Template Measurement Circuit 30 Figure-13 E1 Waveform Template 31 Figure-14 E1 Waveform Template Measurement Circuit 31 Figure-15 Transmit Differential Line Interface with Twisted Pair Cable with Transformer 35 Figure-16 Transmit Differential Line Interface with Coaxial Cable with transformer 35 Figure-17 Transmit Differential Line Interface with Twisted Pair Cable transformer-less, non standard compliant 35 Figure-18 Transmit Single Ended Line Interface with Coaxial Cable with transformer 35 Figure-19 Jitter Attenuator 37 Figure-20 LLOS Indication on Pins 39 Figure-21 TLOS Detection Between Two Channels 41 Figure-22 Pattern Generation 1 43 Figure-23 Pattern Generation 2 43 Figure-24 PRBS / ARB Detection 44 Figure-25 IB Detection 45 Figure-26 Automatic Error Counter Updating 46 Figure-27 Manual Error Counter Updating 46 Figure-28 Priority Of Diagnostic Facilities During Analog Loopback 49 Figure-29 Priority Of Diagnostic Facilities During Manual Remote Loopback 50 Figure-30 Priority Of Diagnostic Facilities During Digital Loopback 51 Figure-31 Priority Of Diagnostic Facilities During Manual Remote Loopback + Manual Digital Loopback 53 Figure-32 Priority Of Diagnostic Facilities During Manual Remote Loopback + Automatic Digital Loopback 53 Figure-33 G.772 Monitoring 54 Figure-34 Automatic JM Updating 55 Figure-35 Manual JM Updating 55 Figure-36 REFA Output Options in Normal Operation 58 Figure-37 REFB Output Options in Normal Operation 59 Figure-38 REFA Output in LLOS Condition When RCLKn Is Selected 59 Figure-39 REFA Output in No CLKA Condition When CLKA Is Selected 60 Figure-40 Interrupt Service Process 63 Figure-41 Reset 64 Figure-42 1+1 HPS Scheme, Differential Interface Shared Common Transformer 66 Figure-43 1:1 HPS Scheme, Differential Interface Individual Transformer 67 Figure-44 1+1 HPS Scheme, E1 75 ohm Single-Ended Interface Shared Common Transformer 68 Figure-45 JTAG Architecture 111 Figure-46 JTAG State Diagram 112 Figure-47 Transmit Clock Timing Diagram 124 Figure-48 Receive Clock Timing Diagram 124 List of Figures February 6, 2009 IDT82P2808 8 +1 CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT Figure-49 CLKE1 Clock Timing Diagram 125 Figure-50 E1 Jitter Tolerance Performance 127 Figure-51 T1/J1 Jitter Tolerance Performance 127 Figure-52 E1 Jitter Transfer Performance 128 Figure-53 T1/J1 Jitter Transfer Performance 128 Figure-54 Read Operation in Serial Microprocessor Interface 129 Figure-55 Write Operation in Serial Microprocessor Interface 129 Figure-56 Timing Diagram 130 Figure-57 Parallel Motorola Non-Multiplexed Microprocessor Interface Read Cycle 131 Figure-58 Parallel Motorola Non-Multiplexed Microprocessor Interface Write Cycle 132 Figure-59 Parallel Intel Non-Multiplexed Microprocessor Interface Read Cycle 133 Figure-60 Parallel Intel Non-Multiplexed Microprocessor Interface Write Cycle 134 Figure-61 Parallel Motorola Multiplexed Microprocessor Interface Read Cycle 135 Figure-62 Parallel Motorola Multiplexed Microprocessor Interface Write Cycle 136 Figure-63 Parallel Intel Multiplexed Microprocessor Interface Read Cycle 137 Figure-64 Parallel Intel Multiplexed Microprocessor Interface Write Cycle 138 Figure-65 JTAG Timing 139 List of Figures February 6, 2009 8 +1 Channel High-Density T1/E1/J1 Line Interface Unit IDT82P2808 Integrates 8+1 channels T1/E1/J1 short haul line interface units for 100 T1, 120 E1, 110 J1 twisted pair cable and 75 E1 coaxial cable applications Per-channel configurable Line Interface options • Supports various line interface options Differential and Single Ended line interfaces true Single Ended termination on primary and secondary side of transformer for E1 75 coaxial cable applications transformer-less for Differential interfaces • Fully integrated and software selectable receive and transmit termination Option 1 Fully Internal Impedance Matching with integrated receive termination resistor Option 2 Partially Internal Impedance Matching with common external resistor for improved device power dissipation Option 3 External impedance Matching termination • Supports global configuration and per-channel configuration to T1, E1 or J1 mode Per-channel programmable features • Provides T1/E1/J1 short haul waveform templates and userprogrammable arbitrary waveform templates • Provides two JAs Jitter Attenuator for each channel of receiver and transmitter • Supports AMI/B8ZS for T1/J1 and AMI/HDB3 for E1 encoding and decoding Per-channel System Interface options • Supports Single Rail, Dual Rail with clock or without clock and sliced system interface • Integrated Clock Recovery for the transmit interface to recover transmit clock from system transmit data Per-channel system and diagnostic functions • Provides transmit driver over-current detection and protection with optional automatic high impedance of transmit interface • Detects and generates PRBS Pseudo Random Bit Sequence , ARB Arbitrary Pattern and IB Inband Loopback in either receive or transmit direction • Provides defect and alarm detection in both receive and transmit directions. Defects include BPV Bipolar Violation /CV Code Violation and EXZ Excessive Zeroes Alarms include LLOS Line LOS , SLOS System LOS , TLOS Transmit LOS and AIS Alarm Indication Signal • Programmable LLOS detection /clear levels. Compliant with ITU and ANSI specifications • Various pattern, defect and alarm reporting options Serial hardware LLOS reporting LLOS, LLOS0 for all 9 channels Configurable per-channel hardware reporting with RMF/TMF Receive /Transmit Multiplex Function Register access to individual registers or 16-bit error counters • Supports Analog Loopback, Digital Loopback and Remote Loopback • Supports T1.102 line monitor Channel 0 monitoring options • Channel 0 can be configured as monitoring channel or regular channel to increase capacity • Supports all internal G.772 Monitoring for Non-Intrusive Monitoring of any of the 8 channels of receiver or transmitter • Jitter Measurement per ITU O.171 Hitless Protection Switching HPS without external Relays • Supports 1+1 and 1:1 hitless protection switching • Asynchronous hardware control OE, RIM for fast global high impedance of receiver and transmitter hot switching between working and backup board • High impedance transmitter and receiver while powered down • Per-channel register control for high impedance, independent for receiver and transmitter Clock Inputs and Outputs • Flexible master clock N x MHz or N x MHz 1 N 8, N is an integer number • Two selectable reference clock outputs from the recovered clock of any of the 9 channels from external clock input from device master clock • Integrated clock synthesizer can multiply or divide the reference clock to a wide range of frequencies 8 KHz, 64 KHz, MHz, MHz, MHz, MHz and MHz • Cascading is provided to select a single reference clock from multiple devices without the need for any external logic ORDERING INFORMATION Device Type XX Package X Process/Temperature Range BLANK Industrial -40 °C to +85 °C Plastic Ball Grid Array 416-pin PBGA, BB416 Green Plastic Ball Grid Array 416-pin PBGA, BBG416 82P2808 8 +1 High-Density T1/E1/J1 Line Interface Unit Data Sheet Document History 01/11/2007 Page 122 02/06/2009 Pages 18, 56, 61 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 1-800-345-7015 or 408-284-8200 fax 408-284-2775 IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. for Tech Support 408-360-1552

PDF Datasheet Preview

8 +1 Channel High-Density T1/E1/J1

Line Interface Unit IDT82P2808

Version 2 February 6, 2009
6024 Silver Creek Valley Road, San Jose, California 95138 Telephone 1-800-345-7015 or 408-284-8200• TWX 910-338-2070
• FAX 408-284-2775

Printed in U.S.A. 2009 Integrated Device Technology, Inc.

DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.

LIFE SUPPORT POLICY Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT. Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

Table of Contents

TABLE OF CONTENTS 3

LIST OF TABLES 7

LIST OF FIGURES 8

FEATURES 10

BLOCK DIAGRAM 12
1 PIN ASSIGNMENT 13
2 PIN DESCRIPTION 14
3 FUNCTIONAL DESCRIPTION 24

T1 / E1 / J1 MODE SELECTION 24 RECEIVE PATH 24

Rx Termination 24 Receive Differential Mode 24 Receive Single Ended Mode 26

Equalizer 27 Line Monitor 27 Receive Sensitivity 27

Slicer 28 Rx Clock & Data Recovery 28 Decoder 28 Receive System Interface 28 Receiver Power Down 29 TRANSMIT PATH 29 Transmit System Interface 29 Tx Clock Recovery 30 Encoder 30 Waveform Shaper 30

Preset Waveform Template 30 User-Programmable Arbitrary Waveform 32 Line Driver 34 Transmit Over Current Protection 34 Tx Termination 34 Transmit Differential Mode 34 Transmit Single Ended Mode 35 Transmitter Power Down 36 Output High-Z on TTIP and TRING 36 JITTER ATTENUATOR RJA & TJA 37

Table of Contents

February 6, 2009

IDT82P2808
8 +1 CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT

DIAGNOSTIC FACILITIES 38 Bipolar Violation BPV / Code Violation CV Detection and BPV Insertion 38 Bipolar Violation BPV / Code Violation CV Detection 38 Bipolar Violation BPV Insertion 38 Excessive Zeroes EXZ Detection 38 Loss of Signal LOS Detection 39 Line LOS LLOS 39 System LOS SLOS 40 Transmit LOS TLOS 41 Alarm Indication Signal AIS Detection and Generation 42 Alarm Indication Signal AIS Detection 42 Alarm Indication Signal AIS Generation 42 PRBS, QRSS, ARB and IB Pattern Generation and Detection 43 Pattern Generation 43 Pattern Detection 44 Error Counter 45 Automatic Error Counter Updating 45 Manual Error Counter Updating 46 Receive /Transmit Multiplex Function RMF / TMF Indication 47 RMFn Indication 47 TMFn Indication 48 Loopback 49 Analog Loopback 49 Remote Loopback 50 Digital Loopback 51 Dual Loopback 52 Channel 0 Monitoring 54 G.772 Monitoring 54 Jitter Measurement JM 55

CLOCK INPUTS AND OUTPUTS 56 Free Running Clock Outputs on CLKT1/CLKE1 56 Clock Outputs on REFA/REFB 57 REFA/REFB in Clock Recovery Mode 57 Frequency Synthesizer for REFA Clock Output 57 Free Run Mode for REFA Clock Output 57 REFA/REFB Driven by External CLKA/CLKB Input 57 REFA and REFB in Loss of Signal LOS or Loss of Clock Condition 57 MCLK, Master Clock Input 61 XCLK, Internal Reference Clock Input 61

INTERRUPT SUMMARY 62
4 MISCELLANEOUS 64

RESET 64 Power-On Reset 65 Hardware Reset 65 Global Software Reset 65

Table of Contents

February 6, 2009

IDT82P2808
8 +1 CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT

Per-Channel Software Reset 65 MICROPROCESSOR INTERFACE 65 POWER UP 66 HITLESS PROTECTION SWITCHING HPS SUMMARY 66
5 PROGRAMMING INFORMATION 69

REGISTER MAP 69 Global Register 69 Per-Channel Register 70

REGISTER DESCRIPTION 73 Global Register 73 Per-Channel Register 81
6 JTAG 111

JTAG INSTRUCTION REGISTER IR 111 JTAG DATA REGISTER 111

Device Identification Register IDR 111 Bypass Register BYP 111 Boundary Scan Register BSR 111 TEST ACCESS PORT TAP CONTROLLER 111
ORDERING INFORMATION 144

Table of Contents

February 6, 2009

List of Tables

Table-1 Operation Mode Selection 24 Table-2 Impedance Matching Value in Receive Differential Mode 25 Table-3 Multiplex Pin Used in Receive System Interface 28 Table-4 Multiplex Pin Used in Transmit System Interface 30 Table-5 PULS[3:0] Setting in T1/J1 Mode 30 Table-6 PULS[3:0] Setting in E1 Mode 31 Table-7 Transmit Waveform Value for T1 0 ~ 133 ft 33 Table-8 Transmit Waveform Value for T1 133 ~ 266 ft 33 Table-9 Transmit Waveform Value for T1 266 ~ 399 ft 33 Table-10 Transmit Waveform Value for T1 399 ~ 533 ft 33 Table-11 Transmit Waveform Value for T1 533 ~ 655 ft 33 Table-12 Transmit Waveform Value for E1 75 ohm 33 Table-13 Transmit Waveform Value for E1 120 ohm 33 Table-14 Transmit Waveform Value for J1 0 ~ 655 ft 33 Table-15 Impedance Matching Value in Transmit Differential Mode 34 Table-16 EXZ Definition 38 Table-17 LLOS Criteria 39 Table-18 SLOS Criteria 40 Table-19 TLOS Detection Between Two Channels 41 Table-20 AIS Criteria 42 Table-21 RMFn Indication 47 Table-22 TMFn Indication 48 Table-23 Clock Output on CLKT1 56 Table-24 Clock Output on CLKE1 56 Table-25 Interrupt Summary 62 Table-26 After Reset Effect Summary 64 Table-27 Microprocessor Interface 65

List of Tables

February 6, 2009

List of Figures

Figure-1 Functional Block Diagram 12 Figure-2 416-Pin PBGA Top View 13 Figure-3 Switch between Impedance Matching Modes 24 Figure-4 Receive Differential Line Interface with Twisted Pair Cable with transformer 25 Figure-5 Receive Differential Line Interface with Coaxial Cable with transformer 25 Figure-6 Receive Differential Line Interface with Twisted Pair Cable transformer-less, non standard compliant 26 Figure-7 Receive Single Ended Line Interface with Coaxial Cable with transformer 26 Figure-8 Receive Single Ended Line Interface with Coaxial Cable transformer-less, non standard compliant 26 Figure-9 Receive Path Monitoring 27 Figure-10 Transmit Path Monitoring 27 Figure-11 DSX-1 Waveform Template 30 Figure-12 T1 Waveform Template Measurement Circuit 30 Figure-13 E1 Waveform Template 31 Figure-14 E1 Waveform Template Measurement Circuit 31 Figure-15 Transmit Differential Line Interface with Twisted Pair Cable with Transformer 35 Figure-16 Transmit Differential Line Interface with Coaxial Cable with transformer 35 Figure-17 Transmit Differential Line Interface with Twisted Pair Cable transformer-less, non standard compliant 35 Figure-18 Transmit Single Ended Line Interface with Coaxial Cable with transformer 35 Figure-19 Jitter Attenuator 37 Figure-20 LLOS Indication on Pins 39 Figure-21 TLOS Detection Between Two Channels 41 Figure-22 Pattern Generation 1 43 Figure-23 Pattern Generation 2 43 Figure-24 PRBS / ARB Detection 44 Figure-25 IB Detection 45 Figure-26 Automatic Error Counter Updating 46 Figure-27 Manual Error Counter Updating 46 Figure-28 Priority Of Diagnostic Facilities During Analog Loopback 49 Figure-29 Priority Of Diagnostic Facilities During Manual Remote Loopback 50 Figure-30 Priority Of Diagnostic Facilities During Digital Loopback 51 Figure-31 Priority Of Diagnostic Facilities During Manual Remote Loopback + Manual Digital Loopback 53 Figure-32 Priority Of Diagnostic Facilities During Manual Remote Loopback + Automatic Digital Loopback 53 Figure-33 G.772 Monitoring 54 Figure-34 Automatic JM Updating 55 Figure-35 Manual JM Updating 55 Figure-36 REFA Output Options in Normal Operation 58 Figure-37 REFB Output Options in Normal Operation 59 Figure-38 REFA Output in LLOS Condition When RCLKn Is Selected 59 Figure-39 REFA Output in No CLKA Condition When CLKA Is Selected 60 Figure-40 Interrupt Service Process 63 Figure-41 Reset 64 Figure-42 1+1 HPS Scheme, Differential Interface Shared Common Transformer 66 Figure-43 1:1 HPS Scheme, Differential Interface Individual Transformer 67 Figure-44 1+1 HPS Scheme, E1 75 ohm Single-Ended Interface Shared Common Transformer 68 Figure-45 JTAG Architecture 111 Figure-46 JTAG State Diagram 112 Figure-47 Transmit Clock Timing Diagram 124 Figure-48 Receive Clock Timing Diagram 124

List of Figures

February 6, 2009

IDT82P2808
8 +1 CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT

Figure-49 CLKE1 Clock Timing Diagram 125 Figure-50 E1 Jitter Tolerance Performance 127 Figure-51 T1/J1 Jitter Tolerance Performance 127 Figure-52 E1 Jitter Transfer Performance 128 Figure-53 T1/J1 Jitter Transfer Performance 128 Figure-54 Read Operation in Serial Microprocessor Interface 129 Figure-55 Write Operation in Serial Microprocessor Interface 129 Figure-56 Timing Diagram 130 Figure-57 Parallel Motorola Non-Multiplexed Microprocessor Interface Read Cycle 131 Figure-58 Parallel Motorola Non-Multiplexed Microprocessor Interface Write Cycle 132 Figure-59 Parallel Intel Non-Multiplexed Microprocessor Interface Read Cycle 133 Figure-60 Parallel Intel Non-Multiplexed Microprocessor Interface Write Cycle 134 Figure-61 Parallel Motorola Multiplexed Microprocessor Interface Read Cycle 135 Figure-62 Parallel Motorola Multiplexed Microprocessor Interface Write Cycle 136 Figure-63 Parallel Intel Multiplexed Microprocessor Interface Read Cycle 137 Figure-64 Parallel Intel Multiplexed Microprocessor Interface Write Cycle 138 Figure-65 JTAG Timing 139

List of Figures

February 6, 2009
8 +1 Channel High-Density T1/E1/J1 Line Interface Unit

IDT82P2808

Integrates 8+1 channels T1/E1/J1 short haul line interface units for 100 T1, 120 E1, 110 J1 twisted pair cable and 75 E1 coaxial cable applications

Per-channel configurable Line Interface options
• Supports various line interface options Differential and Single Ended line interfaces true Single Ended termination on primary and secondary side of transformer for E1 75 coaxial cable applications transformer-less for Differential interfaces
• Fully integrated and software selectable receive and transmit termination Option 1 Fully Internal Impedance Matching with integrated receive termination resistor Option 2 Partially Internal Impedance Matching with common external resistor for improved device power dissipation Option 3 External impedance Matching termination
• Supports global configuration and per-channel configuration to T1, E1 or J1 mode

Per-channel programmable features
• Provides T1/E1/J1 short haul waveform templates and userprogrammable arbitrary waveform templates
• Provides two JAs Jitter Attenuator for each channel of receiver and transmitter
• Supports AMI/B8ZS for T1/J1 and AMI/HDB3 for E1 encoding and decoding

Per-channel System Interface options
• Supports Single Rail, Dual Rail with clock or without clock and sliced system interface
• Integrated Clock Recovery for the transmit interface to recover transmit clock from system transmit data

Per-channel system and diagnostic functions
• Provides transmit driver over-current detection and protection with optional automatic high impedance of transmit interface
• Detects and generates PRBS Pseudo Random Bit Sequence , ARB Arbitrary Pattern and IB Inband Loopback in either receive or transmit direction
• Provides defect and alarm detection in both receive and transmit directions. Defects include BPV Bipolar Violation /CV Code Violation and EXZ Excessive Zeroes Alarms include LLOS Line LOS , SLOS System LOS , TLOS Transmit LOS and AIS Alarm Indication Signal
• Programmable LLOS detection /clear levels. Compliant with ITU and ANSI specifications
• Various pattern, defect and alarm reporting options Serial hardware LLOS reporting LLOS, LLOS0 for all 9 channels Configurable per-channel hardware reporting with RMF/TMF Receive /Transmit Multiplex Function Register access to individual registers or 16-bit error counters
• Supports Analog Loopback, Digital Loopback and Remote Loopback
• Supports T1.102 line monitor

Channel 0 monitoring options
• Channel 0 can be configured as monitoring channel or regular channel to increase capacity
• Supports all internal G.772 Monitoring for Non-Intrusive Monitoring of any of the 8 channels of receiver or transmitter
• Jitter Measurement per ITU O.171

Hitless Protection Switching HPS without external Relays
• Supports 1+1 and 1:1 hitless protection switching
• Asynchronous hardware control OE, RIM for fast global high impedance of receiver and transmitter hot switching between working and backup board
• High impedance transmitter and receiver while powered down
• Per-channel register control for high impedance, independent for receiver and transmitter

Clock Inputs and Outputs
• Flexible master clock N x MHz or N x MHz 1 N 8, N is an integer number
• Two selectable reference clock outputs from the recovered clock of any of the 9 channels from external clock input from device master clock
• Integrated clock synthesizer can multiply or divide the reference clock to a wide range of frequencies 8 KHz, 64 KHz, MHz, MHz, MHz, MHz and MHz
• Cascading is provided to select a single reference clock from multiple devices without the need for any external logic
ORDERING INFORMATION

Device Type

XX Package

X Process/Temperature Range

BLANK

Industrial -40 °C to +85 °C

Plastic Ball Grid Array
416-pin PBGA, BB416

Green Plastic Ball Grid Array
416-pin PBGA, BBG416
82P2808 8 +1 High-Density T1/E1/J1 Line Interface Unit

Data Sheet Document History
01/11/2007 Page 122 02/06/2009 Pages 18, 56, 61

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 1-800-345-7015 or 408-284-8200 fax 408-284-2775

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
for Tech Support 408-360-1552

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT82P2808BBG Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT82P2808BBG 637390