IDT79R4700-133G

IDT79R4700-133G Datasheet


IDT79R4700

Part Datasheet
IDT79R4700-133G IDT79R4700-133G IDT79R4700-133G (pdf)
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IDT79R4700-133DP IDT79R4700-133DP IDT79R4700-133DP
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PDF Datasheet Preview
64-Bit RISC Microprocessor

IDT79R4700

True 64-bit microprocessor 64-bit integer operations 64-bit floating-point operations 64-bit registers 64-bit virtual address space

High-performance microprocessor 260 Dhrystone MIPS at 200MHz 100 peak MFLOP/s at 200MHz Two-way set associative caches Simple 5-stage pipeline

High level of integration 64-bit, 200 MHz integer CPU 64-bit floating-point unit 16KB instruction cache 16KB data cache Flexible MMU with large, fully associative TLB

Low-power operation 3.3V power supply, for the “RV” part 5V power supply, for the “R” part Dynamic power management Standby mode reduces internal power

Fully software & pin-compatible with 40XX Processor Family

Available in 179-pin PGA or 208-pin QFP

Available at 80-200MHz, with mode bit dependent output clock frequencies
64GB physical address space Processor family for a wide variety of embedded
applications LAN switches Routers Color printers

The IDT79R4700 64-bit RISC Microprocessor is both software and pin-compatible with the R4XXX processor family. With 64-bit processing capabilities, the R4700 provides more computational power and data movement bandwidth than is delivered to typical embedded systems by 32-bit processors.

The R4700 is upwardly software compatible with the IDT79R3000 microprocessor family, including the IDTRISController 79R3051 , R3052 , R3041 , R3081 as well as the R4640 , R4650 , RC64474/ 475 and R5000 . An array of development tools facilitates rapid development of R4700-based systems, allowing a variety of customers access to the MIPS Open Architecture philosophy.

Block Diagram

Data Set A Store Buffer

Data Tag A DTLB Physical

Data Tag B

Instruction Set A

SysAD

Write Buffer Read Buffer

Control

Data Set B DBus

Floating-point Register File

Unpacker/Packer

Floating-point Add/Sub/Cvt/Div/Sqrt

Integer Divide

Floating-point/Integer Multiply

Phase Lock Loop, Clocks

Floating-point Control

Address Buffer Instruction Tag A

ITLB Physical Instruction Tag B

Instruction Select Instruction Register

Instruction Set B

IBus

Tag AuxTag Joint TLB

Load Aligner Integer Register File

Integer/Address Adder

Coprocessor 0

Data TLB Virtual DVA

Shifter/Store Aligner

Logic Unit
December 5, 2008 Removed IDT from ordering codes on Ordering Information page.
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December 5, 2008

IDT79R4700

Mode bit

Mode bit
reserved must be zero
14:13

Output driver strength 10 100% strength fastest , 11 83% strength, 00 67% strength, 01 50% strength slowest

Writeback data rate
1 DDx,
2 DDxx,
3 DxDx,
4 DDxxx,
5 DDxxxx,
6 DxxDxx,
8 DxxxDxxx,
reserved
bit 15
0 TClock[0] enabled 1 TClock[0] disabled

Clock divisor
7 reserved
bit 16
0 TClock[1] enabled 1 TClock[1] disabled
0 Little endian,
1 Big endian
bit 17
0 enabled 1 RClock[0] disabled
10:9
00 R4000 compatible,
01 reserved,
10 pipelined writes,
11 write re-issue
bit 18
0 RClock[1] enabled 1 disabled

Disable the timer interrupt on Int[5].
255:19

Reserved must be zero
0 Enabled
1 Disabled
reserved must be zero
Ordering Information
79 YY Configuration

XXXX

Device Type
999 Speed

A Package

Process/ Temperature

Range

Blank

Commercial to Case

PGA 179
208-Pin QFP
80 100 133 150 175 200
4700
80 MHz 100 MHz 133 MHz 150 MHz 175 MHz 200 MHz

Enhanced 64-bit CPU
3.3Vℜ± 5
5.0Vℜ± 5

Valid Combinations
79R4700 - 80, 100, 133 - GH, DP 79RV4700 -100, 133, 150, 175, 200 - GH, DP

PGA, QFP Package PGA, QFP Package

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775

The IDT logo is a trademark of Integrated Device Technology, Inc.
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for Tech Support email phone 408-284-8208

December 5, 2008
More datasheets: IDT5V993A-5QGI8 | IDT5V993A-7QGI | IDT5V993A-7QGI8 | IDT5V993A-2QG | MP3385GF | MP3385GR-P | MP3385GF-Z | MP3385GR-Z | IDT79R4700-133DP | IDT79R4700-100DP


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Datasheet ID: IDT79R4700-133G 637388