IDT79R3041-33J

IDT79R3041-33J Datasheet

IDT79R3041 INTEGRATED RISController FOR LOW-COST SYSTEMS

Part	Datasheet
IDT79R3041-33J	IDT79R3041-33J (pdf)

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IDT79R3041-33J8	IDT79R3041-33J8
IDT79R3041-20PF8	IDT79R3041-20PF8

PDF Datasheet Preview
Integrated Device Technology, Inc. IDT79R3041 INTEGRATED RISController FOR LOW-COST SYSTEMS IDT79R3041 IDT79RV3041 FEATURES: • Instruction set compatible with IDT79R3000A and RISController Family MIPS RISC CPUs • High level of integration minimizes system cost RISC CPU Multiply/divide unit Instruction Cache Data Cache Programmable bus interface Programmable port width support • On-chip instruction and data caches 2KB of Instruction Cache 512B of Data Cache • Flexible bus interface allows simple, low-cost designs Superset pin-compatible with RISController Adds programmable port width interface 8-, 16-, and 32-bit memory sub-regions Adds programmable bus interface timing support Extended address hold, Bus turn around time, Read/write masks • Double-frequency clock input • 16.67MHz, 20MHz, 25MHz and 33MHz operation • 20MIPS at 25MHz • Low cost 84-pin PLCC packaging • On-chip 4-deep write buffer eliminates memory write stalls • On-chip 4-word read buffer supports burst or simple block reads • On-chip DMA arbiter • On-chip 24-bit timer • Boot from 8-bit, 16-bit, or 32-bit wide PROMs • Pin- and software-compatible family includes R3041, R3051, R3052 , and R3081 • Complete software support Optimizing compilers Real-time operating systems Monitors/debuggers Floating Point emulation software Page Description Languages ClkIn Clock Generator Unit Int 5:3 , SInt 2:0 Master Pipeline Control SBrCond 3:2 System Control Coprocessor Exception/Control Registers Bus Interface Registers PortSize Register Counter Registers Integer CPU Core General Registers 32 x 32 Shifter Mult/Div Unit Address Adder PC Control Virtual Address 32 Physical Address Bus Instruction Cache 2kB 32 Data Cache 512B 4-deep Write Buffer Data Unpack Unit Data Bus R3051 Superset Bus Interface Unit 4-deep Read Buffer DMA Arbiter BIU Control Data Pack Unit Timing/ Interface Control Address/ Data configured to operate with either byte ordering convention, and in fact may also be dynamically switched between the two conventions. This facilitates the porting of applications from other processor architectures, and also permits intercommunication between various types of processors and databases. • Data Cache Refill of one or four words The memory system must be capable of performing 4 word transfers to satisfy instruction cache misses and 1 word transfers to satisfy uncached references. The data cache refill size option allows the system designers to choose between one and four word refill on data cache misses, depending on the performance each option brings to their application. • Bus Turn Around speed The R3041 allows the kernel to increase the amount of time between bus transactions when changes in direction of the A/D bus occur e.g., at the end of reads followed by writes . This allows transceivers and buffers to be eliminated from the system. • Extended Address Hold Time The R3041 allows the system designer to increase the amount of hold time available for address latching, thus allowing slower speed low cost address latches, FPGAs and ASICs to be used. • Programmable control signals The R3041 allows the system designer to optimally configure various memory control signals to be active on reads only, writes only, or on both reads and writes. This allows the simplification of external logic, thus reducing system cost. IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS COMMERCIAL TEMPERATURE RANGE • Programmable memory Port Widths The R3041 allows the kernel to partition the physical memory space into various sub-regions, and to individually indicate the port width of these sub-regions. Thus, the bus interface unit can perform data packing and unpacking when communicating with narrow memory sub-regions. For example, these features, can be used to allow the R3041 to interface with narrow 8-bit boot PROMs, or to implement 16-bit only memory systems. THERMAL CONSIDERATIONS The RISController family utilizes special packaging techniques to improve the thermal properties of high-speed processors. Thus, all versions of the RISController family are packaged in cavity down packaging. The lowest cost members of the family use a standard cavity down, injection molded PLCC package the “J” package . This package is used for all speeds of the R3041 family. Higher speed and higher performance members of the RISController family utilize more advanced packaging techniques to dissipate power while remaining both low-cost and pin- and socket- compatible with the PLCC package. Thus, these members of the RISController family are available in the MQUAD package the “MJ” package , which is an all aluminum package with the die attached to a normal copper leadframe mounted to the aluminum casing. The MQUAD package is pin and form compatible with the PLCC package. Thus, designers can choose to utilize this package without changing their PCB. Airflow ft/min ØCA 0 200 400 600 800 1000 "J" Package 26 21 18 16 15 TQFP 40 35 33 31 2905 tbl 02 Table Thermal Resistance ØCA at Various Airflows The members of the RISController family are guaranteed in a case temperature range of 0°C to +85°C. The type of package, speed power of the device, and airflow conditions, affect the equivalent ambient conditions which meet this specification. The equivalent allowable ambient temperature, TA, can be calculated using the thermal resistance from case to ambient ØCA of the given package. The following equation relates ambient and case temperature: TA = TC - P * ØCA where P is the maximum power consumption at hot temperature, calculated by using the maximum Icc specification for the device. Typical values for ØCA at various airflows are shown in Table 2 for the PLCC package. NOTES ON SYSTEM DESIGN The R3041 has been designed to simplify the task of highspeed system design. Thus, set-up and hold-time requirements have been kept to a minimum, allowing a wide variety of system interface strategies. To minimize these AC parameters, the R3041 employs feedback from its SysClk output to the internal bus interface unit. This allows the R3041 to reference input signals to the reference clock seen by the external system. The SysClk output is designed to provide relatively large AC drive to minimize skew due to slow rise or fall times. A typical part will have less than 2ns rise or fall 10% to 90% signal times when driving the test load. Therefore, the system designer should use care when designing for direct SysClk use. Total loading due to devices connected on the signal net and the routing of the net itself should be minimized to ensure the SysClk output has a smooth and rapid transition. Long rise and/or fall times may cause a degradation in the speed capability of an individual device. Similarly, the R3041 employs feedback on its ALE output to ensure adequate address hold time to ALE. The system designer should be careful when designing the ALE net to minimize total loading and to minimize skew between ALE and the A/D bus, which will ensure adequate address access latch time. IDT's field and factory applications groups can provide the system designer with assistance for these and other design issues. IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS PIN CONFIGURATIONS COMMERCIAL TEMPERATURE RANGE A/D 31 A/D 30 A/D 29 A/D 28 A/D 27 VSS VCC A/D 26 A/D 25 A/D 24 A/D 23 A/D 22 A/D 21 VCC VSS A/D 20 A/D 19 A/D 18 A/D 17 A/D 16 A/D 15 ClkIn TriState BE16 1 BE16 0 Addr 1 Addr 0 Int 5 Int 4 Int 3 SInt 2 SInt 1 SInt 0 SBrCond 3 / IOStrobe SBrCond 2 / ExtDataEn 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 IDT R3041/RV3041 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 VSS VCC A/D 14 A/D 13 A/D 12 A/D 11 A/D 10 A/D 9 VCC VSS A/D 8 A/D 7 A/D 6 A/D 5 A/D 4 A/D 3 VSS VCC A/D 2 A/D 1 A/D 0 The byte lanes used during the transfer are a function of the datum size, the memory port width, and the system byte-ordering. Addr 3:0 Low Address 3:0 A 4-bit bus which indicates which word/halfword/byte is currently expected by the processor. For 32-bit port widths, only Addr 3:2 is valid during the transfer for 16-bit port widths, only Addr 3:1 are valid for 8-bit port widths, all of Addr 3:0 are valid. These address lines always contain the address of the current datum to be transferred. In writes and single datum reads, the addresses initially output the specific target address, and will increment if the size of the datum is wider than the target memory port. For quad word reads, these outputs function as a counter starting at '0000', and incrementing according to the width of the memory port. During Reset, the Addr 3:0 pins act as Reset Configuration Mode bit inputs for the BootProm16, BootProm8, ReservedHigh, and ExtAddrHold options. The R3041 Addr 1:0 output pins are designated as the unconnected Rsvd 1:0 pins in the R3051 and R3081. Diag Diagnostic Pin. This output indicates whether the current bus read transaction is due to an on- chip cache miss and whether the read is an instruction or data. It is time multiplexed as described below: Cached/Uncached: During the phase in which the A/D bus presents address information, this pin is an active high output which indicates whether or not the current read is a result of a cache miss. The value of this pin at this time other than in read cycles is undefined. I/D: A high at this time indicates an instruction reference, and a low indicates a data reference. The value of this pin at this time other than in read cycles is undefined. The R3041 Diag output pin is designated as the Diag 1 output pin in the R3051 and R3081. Address Latch Enable Used to indicate that the A/D bus contains valid address information for the bus transaction. This signal is used by external logic to capture the address for the transfer, typically by using transparent latches. DataEn Data Enable This signal indicates that the A/D bus is no longer being driven by the processor during read cycles, and thus the external memory system may enable the drivers of the memory system onto this bus without having a bus conflict occur. During write cycles, or when no bus trans- action is occurring, this signal is negated, thus disabling the external memory drivers. NOTE: Reset Configuration Mode bit input when Reset is asserted, normal signal function when Reset is de-asserted. 2905 tbl 03 IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION Continued : PIN NAME Burst/ WrNear RdCEn SysClk BusReq BusGnt SBrCond 3 / I/O IOStrobe SBrCond 2 / I/O ExtDataEn ORDERING INFORMATION IDT Device Type Speed Package Process/ Temp. Range Blank 'J' 'PF' '16' '20' '25' '33' 79R3041 79RV3041 Commercial Temperature Range 84-Pin PLCC 100-Pin TQFP 16.67MHz 20.00MHz 25.00MHz 33.00MHz 5.0V Integrated RISController for Low-Cost Systems 3.3V Integrated RISController for Low-Cost Systems 2905 drw 32 VALID COMBINATIONS IDT 79R3041 - 16 79R3041 - 20 79R3041 - 25 79R3041 - 33 79RV3041 - 16 79RV3041 - 20 79RV3041 - 25 79RV3041 - 33 TQFP, PLCC Package TQFP, PLCC Package TQFP, PLCC Package PLCC Package Only TQFP, PLCC Package TQFP, PLCC Package TQFP, PLCC Package TQFP, PLCC Package

PDF Datasheet Preview

Integrated Device Technology, Inc.

IDT79R3041 INTEGRATED RISController FOR LOW-COST SYSTEMS

IDT79R3041 IDT79RV3041

FEATURES:
• Instruction set compatible with IDT79R3000A and RISController Family MIPS RISC CPUs
• High level of integration minimizes system cost RISC CPU Multiply/divide unit Instruction Cache Data Cache Programmable bus interface Programmable port width support
• On-chip instruction and data caches 2KB of Instruction Cache 512B of Data Cache
• Flexible bus interface allows simple, low-cost designs Superset pin-compatible with RISController Adds programmable port width interface 8-, 16-, and 32-bit memory sub-regions Adds programmable bus interface timing support Extended address hold, Bus turn around time, Read/write masks
• Double-frequency clock input
• 16.67MHz, 20MHz, 25MHz and 33MHz operation
• 20MIPS at 25MHz
• Low cost 84-pin PLCC packaging
• On-chip 4-deep write buffer eliminates memory write stalls
• On-chip 4-word read buffer supports burst or simple block
reads
• On-chip DMA arbiter
• On-chip 24-bit timer
• Boot from 8-bit, 16-bit, or 32-bit wide PROMs
• Pin- and software-compatible family includes R3041, R3051,

R3052 , and R3081
• Complete software support

Optimizing compilers Real-time operating systems Monitors/debuggers Floating Point emulation software Page Description Languages

ClkIn

Clock Generator

Unit

Int 5:3 , SInt 2:0

Master Pipeline Control SBrCond 3:2

System Control Coprocessor

Exception/Control Registers

Bus Interface Registers

PortSize Register Counter Registers

Integer CPU Core

General Registers 32 x 32

Shifter

Mult/Div Unit

Address Adder PC Control

Virtual Address 32

Physical Address Bus

Instruction Cache 2kB
32 Data Cache 512B
4-deep Write Buffer

Data Unpack

Unit

Data Bus

R3051 Superset Bus Interface Unit
4-deep Read Buffer

DMA Arbiter

BIU Control

Data Pack Unit

Timing/ Interface Control

Address/ Data
configured to operate with either byte ordering convention, and in fact may also be dynamically switched between the two conventions. This facilitates the porting of applications from other processor architectures, and also permits intercommunication between various types of processors and databases.
• Data Cache Refill of one or four words The memory system must be capable of performing 4 word transfers to satisfy instruction cache misses and 1 word transfers to satisfy uncached references. The data cache refill size option allows the system designers to choose between one and four word refill on data cache misses, depending on the performance each option brings to their application.
• Bus Turn Around speed The R3041 allows the kernel to increase the amount of time between bus transactions when changes in direction of the A/D bus occur e.g., at the end of reads followed by writes . This allows transceivers and buffers to be eliminated from the system.
• Extended Address Hold Time The R3041 allows the system designer to increase the amount of hold time available for address latching, thus allowing slower speed low cost address latches, FPGAs and ASICs to be used.
• Programmable control signals The R3041 allows the system designer to optimally configure various memory control signals to be active on reads only, writes only, or on both reads and writes. This allows the simplification of external logic, thus reducing system cost.

IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS

COMMERCIAL TEMPERATURE RANGE
• Programmable memory Port Widths The R3041 allows the kernel to partition the physical memory space into various sub-regions, and to individually indicate the port width of these sub-regions. Thus, the bus interface unit can perform data packing and unpacking when communicating with narrow memory sub-regions. For example, these features, can be used to allow the R3041 to interface with narrow 8-bit boot PROMs, or to implement 16-bit only memory systems.

THERMAL CONSIDERATIONS

The RISController family utilizes special packaging techniques to improve the thermal properties of high-speed processors. Thus, all versions of the RISController family are packaged in cavity down packaging.

The lowest cost members of the family use a standard cavity down, injection molded PLCC package the “J” package . This package is used for all speeds of the R3041 family.

Higher speed and higher performance members of the RISController family utilize more advanced packaging techniques to dissipate power while remaining both low-cost and pin- and socket- compatible with the PLCC package. Thus, these members of the RISController family are available in the MQUAD package the “MJ” package , which is an all aluminum package with the die attached to a normal copper leadframe mounted to the aluminum casing. The MQUAD package is pin and form compatible with the PLCC package. Thus, designers can choose to utilize this package without changing their PCB.

Airflow ft/min
ØCA
0 200 400 600 800 1000
"J" Package
26 21 18 16 15

TQFP
40 35 33 31
2905 tbl 02

Table Thermal Resistance ØCA at Various Airflows

The members of the RISController family are guaranteed in a case temperature range of 0°C to +85°C. The type of package, speed power of the device, and airflow conditions, affect the equivalent ambient conditions which meet this specification.

The equivalent allowable ambient temperature, TA, can be calculated using the thermal resistance from case to ambient ØCA of the given package. The following equation relates ambient and case temperature:

TA = TC - P * ØCA where P is the maximum power consumption at hot temperature, calculated by using the maximum Icc specification for the device.

Typical values for ØCA at various airflows are shown in Table 2 for the PLCC package.

NOTES ON SYSTEM DESIGN

The R3041 has been designed to simplify the task of highspeed system design. Thus, set-up and hold-time requirements have been kept to a minimum, allowing a wide variety of system interface strategies.

To minimize these AC parameters, the R3041 employs feedback from its SysClk output to the internal bus interface unit. This allows the R3041 to reference input signals to the reference clock seen by the external system. The SysClk output is designed to provide relatively large AC drive to minimize skew due to slow rise or fall times. A typical part will have less than 2ns rise or fall 10% to 90% signal times when driving the test load.

Therefore, the system designer should use care when designing for direct SysClk use. Total loading due to devices connected on the signal net and the routing of the net itself should be minimized to ensure the SysClk output has a smooth and rapid transition. Long rise and/or fall times may cause a degradation in the speed capability of an individual device.

Similarly, the R3041 employs feedback on its ALE output to ensure adequate address hold time to ALE. The system designer should be careful when designing the ALE net to minimize total loading and to minimize skew between ALE and the A/D bus, which will ensure adequate address access latch time.

IDT's field and factory applications groups can provide the system designer with assistance for these and other design issues.

IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS

PIN CONFIGURATIONS

COMMERCIAL TEMPERATURE RANGE

A/D 31 A/D 30 A/D 29 A/D 28 A/D 27 VSS VCC A/D 26 A/D 25 A/D 24 A/D 23 A/D 22 A/D 21 VCC VSS A/D 20 A/D 19 A/D 18 A/D 17 A/D 16 A/D 15

ClkIn

TriState BE16 1 BE16 0

Addr 1

Addr 0

Int 5

Int 4 Int 3 SInt 2 SInt 1 SInt 0 SBrCond 3 / IOStrobe SBrCond 2 / ExtDataEn
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75

IDT R3041/RV3041
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

VSS VCC A/D 14 A/D 13 A/D 12 A/D 11 A/D 10 A/D 9 VCC VSS A/D 8 A/D 7 A/D 6 A/D 5 A/D 4 A/D 3 VSS VCC A/D 2 A/D 1 A/D 0
The byte lanes used during the transfer are a function of the datum size, the memory port width, and the system byte-ordering.

Addr 3:0

Low Address 3:0 A 4-bit bus which indicates which word/halfword/byte is currently expected by the processor. For 32-bit port widths, only Addr 3:2 is valid during the transfer for 16-bit port widths, only Addr 3:1 are valid for 8-bit port widths, all of Addr 3:0 are valid. These address lines always contain the address of the current datum to be transferred. In writes and single datum reads, the addresses initially output the specific target address, and will increment if the size of the datum is wider than the target memory port. For quad word reads, these outputs function as a counter starting at '0000', and incrementing according to the width of the memory port.

During Reset, the Addr 3:0 pins act as Reset Configuration Mode bit inputs for the BootProm16, BootProm8, ReservedHigh, and ExtAddrHold options.

The R3041 Addr 1:0 output pins are designated as the unconnected Rsvd 1:0 pins in the R3051 and R3081.

Diag

Diagnostic Pin. This output indicates whether the current bus read transaction is due to an on-
chip cache miss and whether the read is an instruction or data. It is time multiplexed as described below:

Cached/Uncached:

During the phase in which the A/D bus presents address information, this pin is an active high output which indicates whether or not the current read is a result of a cache miss. The value of this pin at this time other than in read cycles is undefined.

I/D:

A high at this time indicates an instruction reference, and a low indicates
a data reference. The value of this pin at this time other than in read
cycles is undefined.

The R3041 Diag output pin is designated as the Diag 1 output pin in the R3051 and R3081.

Address Latch Enable Used to indicate that the A/D bus contains valid address information for
the bus transaction. This signal is used by external logic to capture the address for the transfer, typically
by using transparent latches.

DataEn

Data Enable This signal indicates that the A/D bus is no longer being driven by the processor
during read cycles, and thus the external memory system may enable the drivers of the memory
system onto this bus without having a bus conflict occur. During write cycles, or when no bus
trans-
action is occurring, this signal is negated, thus disabling the external memory drivers.

NOTE:

Reset Configuration Mode bit input when Reset is asserted, normal signal function when Reset is de-asserted.
2905 tbl 03

IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION Continued :

PIN NAME

Burst/

WrNear

RdCEn

SysClk

BusReq

BusGnt

SBrCond 3 / I/O

IOStrobe

SBrCond 2 / I/O

ExtDataEn
ORDERING INFORMATION

IDT Device Type

Speed Package Process/

Temp. Range

Blank
'J' 'PF'
'16' '20' '25' '33'
79R3041
79RV3041

Commercial Temperature Range 84-Pin PLCC 100-Pin TQFP
16.67MHz 20.00MHz 25.00MHz 33.00MHz
5.0V Integrated RISController for Low-Cost Systems 3.3V Integrated RISController for Low-Cost Systems
2905 drw 32

VALID COMBINATIONS

IDT 79R3041 - 16 79R3041 - 20 79R3041 - 25 79R3041 - 33 79RV3041 - 16 79RV3041 - 20 79RV3041 - 25 79RV3041 - 33

TQFP, PLCC Package TQFP, PLCC Package TQFP, PLCC Package PLCC Package Only TQFP, PLCC Package TQFP, PLCC Package TQFP, PLCC Package TQFP, PLCC Package

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT79R3041-33J Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT79R3041-33J 637384