IDT74FCT88915TT70PY
IDT74FCT88915TT70PY Datasheet
IDT74FCT88915TT LOW SKEW PLL-BASED CMOS CLOCK DRIVER
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IDT74FCT88915TT70PY |
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| IDT74FCT88915TT LOW SKEW PLL-BASED CMOS CLOCK DRIVER LOW SKEW PLL-BASED CMOS CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE IDT74FCT88915TT 55/70/100/133 FEATURES: • MICRON CMOS Technology • Input frequency range 10MHz f2Q Max. spec FREQ_SEL = HIGH • Max. output frequency 133MHz • Pin and function compatible with MC88915 • Five non-inverting outputs, one inverting output, one 2x output, one ÷2 output all outputs are TTL-compatible • Output Skew < 500ps max. • Duty cycle distortion < 500ps max. • Part-to-part skew 0.55ns from tPD max. spec • drive at TTL output voltage levels • Available in PLCC and SSOP packages DESCRIPTION: The FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting in essentially zero delay across the device. The PLL consists of the phase/frequency detector, charge pump, loop filter and VCO. The VCO is designed to run optimally between 20MHz and f2Q Max. The FCT88915TT provides eight outputs with 500ps skew. The Q5 output is inverted from the Q outputs. The 2Q runs at twice the Q frequency and Q/2 runs at half the Q frequency. The FREQ_SEL control provides an additional ÷ 2 option in the output path. PLL _EN allows bypassing of the PLL, which is useful in static test modes. When PLL_EN is low, SYNC input may be used as a test clock. In this test mode, the input frequency is not limited to the specified range and the polarity of outputs is complementary to that in normal operation PLL_EN = The LOCK output attains logic high when the PLL is in steady-state phase and frequency lock. The FCT88915TT requires external loop filter components as recommended in Figure FUNCTIONAL BLOCK DIAGRAM FEEDBACK SYNC 0 SYNC 1 REF_SEL PLL_EN FREQ_SEL RST Phase/Freq. Detector 01 Mux Divide -By-2 ÷ 1 ÷ 2 Charge Pump The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE 1 2001 Integrated Device Technology, Inc. Voltage Controlled O scila to r DQ CP R Q DQ CP R DQ CP R DQ CP R DQ CP R DQ CP R DQ CP R LOCK LF 2Q Q0 Q1 Q2 Q3 Q4 Q5 Q/2 MARCH 2001 DSC-4245/4 IDT74FCT88915TT LOW SKEW PLL-BASED CMOS CLOCK DRIVER PIN CONFIGURATIONS COMMERCIAL TEMPERATURE RANGE RST VCC Q5 GND Q4 VCC 2Q 4 3 2 1 28 27 26 FEEDBK 5 25 Q/2 REF_SEL 6 ORDERING INFORMATION IDT XX FCT XXXX Temp. Range Device Type Speed Package COMMERCIAL TEMPERATURE RANGE J JG PY PYG Plastic Leaded Chip Carrier PLCC - Green Small Shrink Outline IC SSOP - Green 55 1 70 1 100 1 133 1 55MHz Max. frequency 70MHz Max. frequency 100MHz Max. frequency 133MHz Max. frequency 88915TT Low Skew PLL-Based CMOS Clock Driver 0°C to +70°C NOTE When ordering GREEN packages, replace this numeric value with the equivalent letter below. A= 55 MHz B= 70 MHz C= 100 MHz D= 133 MHz For example, to order a 133MHz version, Green PLCC, the nomenclature would be 74FCT88915TTDPYG. CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support: |
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