IDT72V7230L15BBGI

IDT72V7230L15BBGI Datasheet

IDT72V7230, IDT72V7240 IDT72V7250, IDT72V7260 IDT72V7270, IDT72V7280 IDT72V7290, IDT72V72100

Part	Datasheet
IDT72V7230L15BBGI	IDT72V7230L15BBGI (pdf)

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IDT72V7240L10BB	IDT72V7240L10BB
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IDT72V7260L10BB	IDT72V7260L10BB
IDT72V7250L15BB	IDT72V7250L15BB
IDT72V7270L15BB	IDT72V7270L15BB
IDT72V7240L15BB	IDT72V7240L15BB
IDT72V7280L10BB	IDT72V7280L10BB
IDT72V7230L15BB	IDT72V7230L15BB
IDT72V7230L10BBG	IDT72V7230L10BBG
IDT72V7230L10BB	IDT72V7230L10BB
IDT72V72100L15BB	IDT72V72100L15BB
IDT72V72100L10BBG	IDT72V72100L10BBG
IDT72V72100L10BB	IDT72V72100L10BB
IDT72V7250L10BB	IDT72V7250L10BB
IDT72V7290L10BB	IDT72V7290L10BB
IDT72V7280L10BBG	IDT72V7280L10BBG
IDT72V7290L15BB	IDT72V7290L15BB
IDT72V7270L10BB	IDT72V7270L10BB
IDT72V7290L10BBG	IDT72V7290L10BBG
IDT72V7280L15BB	IDT72V7280L15BB

PDF Datasheet Preview
VOLT HIGH-DENSITY SUPERSYNC II 72-BIT FIFO 512 x 72, 1,024 x 72 2,048 x 72, 4,096 x 72 8,192 x 72, 16,384 x 72 32,768 x 72, 65,536 x 72 IDT72V7230, IDT72V7240 IDT72V7250, IDT72V7260 IDT72V7270, IDT72V7280 IDT72V7290, IDT72V72100 FEATURES: • Choose among the following memory organizations IDT72V7230 512 x 72 IDT72V7240 1,024 x 72 IDT72V7250 2,048 x 72 IDT72V7260 4,096 x 72 IDT72V7270 8,192 x 72 IDT72V7280 16,384 x 72 IDT72V7290 32,768 x 72 IDT72V72100 65,536 x 72 • 100 MHz operation 10 ns read/write cycle time • User selectable input and output port bus-sizing - x72 in to x72 out - x72 in to x36 out - x72 in to x18 out - x36 in to x72 out - x18 in to x72 out • Big-Endian/Little-Endian user selectable word representation • Fixed, low first word latency • Zero latency retransmit • Auto power down minimizes standby power consumption FUNCTIONAL BLOCK DIAGRAM • Master Reset clears entire FIFO • Partial Reset clears data, but retains programmable settings • Empty, Full and Half-Full flags signal FIFO status • Programmable Almost-Empty and Almost-Full flags, each flag can default to one of eight preselected offsets • Selectable synchronous/asynchronous timing modes for AlmostEmpty and Almost-Full flags • Program programmable flags by either serial or parallel means • Select IDT Standard timing using EF and FF flags or First Word Fall Through timing using OR and IR flags • Output enable puts data outputs into high impedance state • Easily expandable in depth and width • Independent Read and Write Clocks permit reading and writing simultaneously • Asynchronous operation of Output Enable, OE • Read Chip Select RCS on Read Side • Available in a 256-pin Fine Pitch Ball Grid Array package PBGA • Features JTAG Boundary Scan • High-performance submicron CMOS technology • Industrial temperature range to +85°C is available WEN WCLK D0 -Dn x72, x36 or x18 LD SEN SCLK INPUT REGISTER OFFSET REGISTER WRITE CONTROL LOGIC BM IW OW MRS PRS TCK TRST TMS TDO TDI WRITE POINTER CONTROL LOGIC BUS CONFIGURATION RESET LOGIC JTAG CONTROL BOUNDARY SCAN RAM ARRAY 512 x 72 1,024 x 72 2,048 x 72 4,096 x 72 8,192 x 72 16,384 x 72 32,768 x 72 65,536 x 72 OUTPUT REGISTER OE Q0 -Qn x72, x36 or x18 FLAG LOGIC READ POINTER FF/IR PAF EF/OR PAE HF FWFT/SI PFM FSEL0 ORDERING INFORMATION IDT Device Type X Power XX Speed X Package NOTE Industrial temperature range is available by special order. Process / Temperature Range BLANK 10 15 72V7230 72V7240 72V7250 72V7260 72V7270 72V7280 72V7290 72V72100 Commercial 0°C to +70°C Fine Pitch Ball Grid Array PBGA, BB256−1 Commercial Clock Cycle Time tCLK Speed in Nanoseconds Low Power 512 x 72 3.3V SuperSync II FIFO 1,024 x 72 3.3V SuperSync II FIFO 2,048 x 72 3.3V SuperSync II FIFO 4,096 x 72 3.3V SuperSync II FIFO 8,192 x 72 3.3V SuperSync II FIFO 16,384 x 72 3.3V SuperSync II FIFO 32,768 x 72 3.3V SuperSync II FIFO 65,536 x 72 3.3V SuperSync II FIFO 4680 drw35 DATASHEET DOCUMENT HISTORY 06/01/2000 pgs. 1, 2, 3, 7, 33, 34, 34, 35, 38, 41, and 11/01/2000 pgs. 1, 2, and 01/10/2001 pg. 04/12/2001 pgs. 3, 4, 5, 17, 26, and 05/01/2001 pg. 10/04/2001 pg. 12/16/2002 pgs. 1, 4, 6, 22, 24, and 02/11/2003 pgs. 6, and 09/29/2003 pg. 12/17/2003 pg. CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support 408-360-1753 email:

PDF Datasheet Preview

VOLT HIGH-DENSITY SUPERSYNC II 72-BIT FIFO 512 x 72, 1,024 x 72 2,048 x 72, 4,096 x 72 8,192 x 72, 16,384 x 72 32,768 x 72, 65,536 x 72

IDT72V7230, IDT72V7240 IDT72V7250, IDT72V7260 IDT72V7270, IDT72V7280 IDT72V7290, IDT72V72100

FEATURES:
• Choose among the following memory organizations IDT72V7230 512 x 72 IDT72V7240 1,024 x 72 IDT72V7250 2,048 x 72 IDT72V7260 4,096 x 72 IDT72V7270 8,192 x 72 IDT72V7280 16,384 x 72 IDT72V7290 32,768 x 72 IDT72V72100 65,536 x 72
• 100 MHz operation 10 ns read/write cycle time
• User selectable input and output port bus-sizing
- x72 in to x72 out - x72 in to x36 out - x72 in to x18 out - x36 in to x72 out - x18 in to x72 out
• Big-Endian/Little-Endian user selectable word representation
• Fixed, low first word latency
• Zero latency retransmit
• Auto power down minimizes standby power consumption

FUNCTIONAL BLOCK DIAGRAM
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
• Selectable synchronous/asynchronous timing modes for AlmostEmpty and Almost-Full flags
• Program programmable flags by either serial or parallel means
• Select IDT Standard timing using EF and FF flags or First Word

Fall Through timing using OR and IR flags
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• Independent Read and Write Clocks permit reading and writing
simultaneously
• Asynchronous operation of Output Enable, OE
• Read Chip Select RCS on Read Side
• Available in a 256-pin Fine Pitch Ball Grid Array package PBGA
• Features JTAG Boundary Scan
• High-performance submicron CMOS technology
• Industrial temperature range to +85°C is available

WEN WCLK

D0 -Dn x72, x36 or x18

LD SEN SCLK

INPUT REGISTER

OFFSET REGISTER

WRITE CONTROL LOGIC

BM IW OW

MRS PRS

TCK TRST

TMS TDO TDI

WRITE POINTER

CONTROL LOGIC

BUS CONFIGURATION

RESET LOGIC

JTAG CONTROL BOUNDARY SCAN

RAM ARRAY 512 x 72
1,024 x 72 2,048 x 72 4,096 x 72 8,192 x 72 16,384 x 72 32,768 x 72 65,536 x 72

OUTPUT REGISTER

OE Q0 -Qn x72, x36 or x18

FLAG LOGIC

READ POINTER

FF/IR PAF EF/OR PAE HF FWFT/SI PFM

FSEL0
ORDERING INFORMATION

IDT Device Type

X Power

XX Speed

X Package

NOTE Industrial temperature range is available by special order.

Process / Temperature

Range

BLANK
10 15
72V7230 72V7240 72V7250 72V7260 72V7270 72V7280 72V7290 72V72100

Commercial 0°C to +70°C

Fine Pitch Ball Grid Array PBGA, BB256−1

Commercial

Clock Cycle Time tCLK Speed in Nanoseconds

Low Power
512 x 72 3.3V SuperSync II FIFO 1,024 x 72 3.3V SuperSync II FIFO 2,048 x 72 3.3V SuperSync II FIFO 4,096 x 72 3.3V SuperSync II FIFO 8,192 x 72 3.3V SuperSync II FIFO 16,384 x 72 3.3V SuperSync II FIFO 32,768 x 72 3.3V SuperSync II FIFO 65,536 x 72 3.3V SuperSync II FIFO
4680 drw35

DATASHEET DOCUMENT HISTORY
06/01/2000 pgs. 1, 2, 3, 7, 33, 34, 34, 35, 38, 41, and 11/01/2000 pgs. 1, 2, and 01/10/2001 pg. 04/12/2001 pgs. 3, 4, 5, 17, 26, and 05/01/2001 pg. 10/04/2001 pg. 12/16/2002 pgs. 1, 4, 6, 22, 24, and 02/11/2003 pgs. 6, and 09/29/2003 pg. 12/17/2003 pg.

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775
for Tech Support 408-360-1753
email:

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT72V7230L15BBGI Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT72V7230L15BBGI 637364