IDT72V36104L10PF

IDT72V36104L10PF Datasheet

IDT72V3684

Part	Datasheet
IDT72V36104L10PF	IDT72V36104L10PF (pdf)

Related Parts	Information
IDT72V36104L15PF	IDT72V36104L15PF
IDT72V36104L10PF8	IDT72V36104L10PF8
IDT72V3684L10PF	IDT72V3684L10PF
IDT72V3684L10PF8	IDT72V3684L10PF8
IDT72V36104L15PF8	IDT72V36104L15PF8
IDT72V3684L15PF8	IDT72V3684L15PF8
IDT72V3684L15PF	IDT72V3684L15PF
IDT72V3694L10PF	IDT72V3694L10PF
IDT72V3694L10PF8	IDT72V3694L10PF8
IDT72V3694L10PFG	IDT72V3694L10PFG
IDT72V3694L10PFG8	IDT72V3694L10PFG8
IDT72V3694L15PF	IDT72V3694L15PF
IDT72V3694L15PF8	IDT72V3694L15PF8
IDT72V3684L10PFG	IDT72V3684L10PFG

PDF Datasheet Preview
VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING 16,384 x 36 x 2 IDT72V3684 32,768 x 36 x 2 IDT72V3694 65,536 x 36 x 2 IDT72V36104 • Memory storage capacity IDT72V3684 16,384 x 36 x 2 IDT72V3694 32,768 x 36 x 2 IDT72V36104 65,536 x 36 x 2 • Clock frequencies up to 100 MHz 6.5ns access time • Two independent clocked FIFOs buffering data in opposite directions • Select IDT Standard timing using EFA, EFB, FFA, and FFB flags functions or First Word Fall Through Timing using ORA, ORB, IRA, and IRB flag functions • Programmable Almost-Empty and Almost-Full flags each has five default offsets 8, 16, 64, 256 and 1,024 • Serial or parallel programming of partial flags • Retransmit Capability • Port B bus sizing of 36 bits long word , 18 bits word and 9 bits byte • Big- or Little-Endian format for word and byte bus sizes • Master Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings • Mailbox bypass registers for each FIFO • Free-running CLKA and CLKB may be asynchronous or coincident simultaneous reading and writing of data on a single clock edge is permitted • Auto power down minimizes power dissipation • Available in space saving 128-pin Thin Quad Flatpack TQFP • Pin compatible to the lower density parts, IDT72V3624/72V3634/ 72V3644/72V3654/72V3664/72V3674 • Industrial temperature range to +85°C is available • Green parts available, see ordering information FUNCTIONAL BLOCK DIAGRAM Input Register Output BusMatching Output Register CLKA CSA W/RA ENA MBA MRS1 PRS1 FFA/IRA AFA FS2 FS0/SD FS1/SEN A0-A35 EFA/ORA Port-A Control Logic FIFO1, Mail1 Reset Logic RT1 RTM RT2 FIFO1 and FIFO2 Retransmit Logic Mail 1 Register RAM ARRAY 16,384 x 36 32,768 x 36 65,536 x 36 FIFO1 Write Pointer Read Pointer Status Flag Logic Programmable Flag Offset Registers Timing Mode 16 FIFO2 Status Flag Logic Read Pointer Write Pointer RAM ARRAY 36 16,384 x 36 32,768 x 36 65,536 x 36 Output Register Input BusMatching Input Register MBF2 Mail 2 Register IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncBiFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. MBF1 EFB/ORB AEB ORDERING INFORMATION Device Type Power Speed Package Process/ Temperature Range BLANK Commercial 0oC to +70oC Green Thin Quad Flat Pack TQFP, PK128-1 10 15 Commercial Only Clock Cycle Time tCLK Speed in Nanoseconds Low Power 72V3684 16,384 x 36 x 2 3.3V SyncBiFIFO with Bus-Matching 72V3694 32,768 x 36 x 2 3.3V SyncBiFIFO with Bus-Matching 72V36104 65,536 x 36 x 2 3.3V SyncBiFIFO with Bus-Matching NOTES Industrial temperature range is available by special order. Green parts available. For specific speeds and packages contact your sales office. 4677 drw36 DATASHEET DOCUMENT HISTORY 10/31/2000 12/14/2000 02/08/2001 03/27/2001 11/04/2003 05/27/2008 02/05/2009 pgs. 1, 6, 8, 9, 12 and 36 pgs. 4 and pgs. 5 and pgs. 6 and pg. pg. 1, 6, and pg. CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support 408-360-1753 email:

PDF Datasheet Preview

VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING
16,384 x 36 x 2

IDT72V3684
32,768 x 36 x 2

IDT72V3694
65,536 x 36 x 2

IDT72V36104
• Memory storage capacity IDT72V3684 16,384 x 36 x 2 IDT72V3694 32,768 x 36 x 2 IDT72V36104 65,536 x 36 x 2
• Clock frequencies up to 100 MHz 6.5ns access time
• Two independent clocked FIFOs buffering data in opposite
directions
• Select IDT Standard timing using EFA, EFB, FFA, and FFB flags
functions or First Word Fall Through Timing using ORA, ORB, IRA, and IRB flag functions
• Programmable Almost-Empty and Almost-Full flags each has five default offsets 8, 16, 64, 256 and 1,024
• Serial or parallel programming of partial flags
• Retransmit Capability
• Port B bus sizing of 36 bits long word , 18 bits word and 9 bits byte
• Big- or Little-Endian format for word and byte bus sizes
• Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
• Mailbox bypass registers for each FIFO
• Free-running CLKA and CLKB may be asynchronous or coincident
simultaneous reading and writing of data on a single clock edge is permitted
• Auto power down minimizes power dissipation
• Available in space saving 128-pin Thin Quad Flatpack TQFP
• Pin compatible to the lower density parts, IDT72V3624/72V3634/ 72V3644/72V3654/72V3664/72V3674
• Industrial temperature range to +85°C is available
• Green parts available, see ordering information

FUNCTIONAL BLOCK DIAGRAM

Input Register Output BusMatching Output Register

CLKA CSA

W/RA ENA MBA

MRS1 PRS1

FFA/IRA AFA

FS2 FS0/SD FS1/SEN

A0-A35 EFA/ORA

Port-A Control Logic

FIFO1, Mail1 Reset Logic

RT1 RTM RT2

FIFO1 and FIFO2 Retransmit Logic

Mail 1 Register

RAM ARRAY
16,384 x 36
32,768 x 36
65,536 x 36

FIFO1

Write Pointer

Read Pointer

Status Flag Logic

Programmable Flag Offset Registers

Timing Mode
16 FIFO2

Status Flag Logic

Read Pointer

Write Pointer

RAM ARRAY
36 16,384 x 36
32,768 x 36
65,536 x 36

Output Register Input BusMatching

Input Register

MBF2

Mail 2 Register

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncBiFIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.

MBF1

EFB/ORB AEB
ORDERING INFORMATION

Device Type Power Speed Package

Process/ Temperature

Range

BLANK Commercial 0oC to +70oC

Green

Thin Quad Flat Pack TQFP, PK128-1
10 15

Commercial Only

Clock Cycle Time tCLK Speed in Nanoseconds

Low Power
72V3684 16,384 x 36 x 2 3.3V SyncBiFIFO with Bus-Matching
72V3694 32,768 x 36 x 2 3.3V SyncBiFIFO with Bus-Matching 72V36104 65,536 x 36 x 2 3.3V SyncBiFIFO with Bus-Matching

NOTES Industrial temperature range is available by special order. Green parts available. For specific speeds and packages contact your sales office.
4677 drw36

DATASHEET DOCUMENT HISTORY
10/31/2000 12/14/2000 02/08/2001 03/27/2001 11/04/2003 05/27/2008 02/05/2009
pgs. 1, 6, 8, 9, 12 and 36 pgs. 4 and pgs. 5 and pgs. 6 and pg. pg. 1, 6, and pg.

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775
for Tech Support 408-360-1753
email:

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT72V36104L10PF Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT72V36104L10PF 637361