IDT72V3683L15PF8
IDT72V3683L15PF8 Datasheet
IDT72V3683 IDT72V3693 IDT72V36103
| Part | Datasheet |
|---|---|
IDT72V3683L15PF8 |
IDT72V3683L15PF8 (pdf) |
| Related Parts | Information |
|---|---|
IDT72V36103L15PF8 |
IDT72V36103L15PF8 |
IDT72V36103L15PF |
IDT72V36103L15PF |
IDT72V36103L10PF8 |
IDT72V36103L10PF8 |
IDT72V36103L10PF |
IDT72V36103L10PF |
IDT72V3683L15PF |
IDT72V3683L15PF |
IDT72V3693L10PF |
IDT72V3693L10PF |
IDT72V3693L10PF8 |
IDT72V3693L10PF8 |
IDT72V3693L15PF |
IDT72V3693L15PF |
IDT72V3693L15PF8 |
IDT72V3693L15PF8 |
IDT72V3683L10PF |
IDT72V3683L10PF |
IDT72V3683L10PF8 |
IDT72V3683L10PF8 |
| PDF Datasheet Preview |
|---|
| VOLT CMOS SyncFIFOTM WITH BUS-MATCHING 16,384 x 36 32,768 x 36 65,536 x 36 IDT72V3683 IDT72V3693 IDT72V36103 • Memory storage capacity IDT72V3683 16,384 x 36 IDT72V3693 32,768 x 36 IDT72V36103 65,536 x 36 • Clock frequencies up to 100 MHz ns access time • Clocked FIFO buffering data from Port A to Port B • IDT Standard timing using EF and FF or First Word Fall Through Timing using OR and IR flag functions • Programmable Almost-Empty and Almost-Full flags each has five default offsets 8, 16, 64, 256 and 1,024 • Serial or parallel programming of partial flags • Port B bus sizing of 36 bits long word , 18 bits word and 9 bits byte • Big- or Little-Endian format for word and byte bus sizes • Retransmit Capability • Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings • Mailbox bypass registers for each FIFO • Free-running CLKA and CLKB may be asynchronous or coincident simultaneous reading and writing of data on a single clock edge is permitted • Easily expandable in width and depth • Auto power down minimizes power dissipation • Available in a space-saving 128-pin Thin Quad Flatpack TQFP • Pin compatible with the lower density parts, IDT72V3623/ 72V3633/72V3643/72V3653/72V3663/72V3673 • Industrial temperature range to +85°C is available • Green parts available, see ordering information FUNCTIONAL BLOCK DIAGRAM CLKA CSA W/RA ENA MBA Port-A Control Logic RS1 RS2 PRS RT RTM FIFO1 Mail1, Mail2, Reset Logic FIFO Retransmit Logic A0-A35 Mail 1 Register RAM ARRAY 16,384 x 36 32,768 x 36 65,536 x 36 Write Pointer Read Pointer Input Register BusMatching Output Register MBF1 B0-B35 FF/IR AF Status Flag Logic EF/OR AE FS2 FS0/SD FS1/SEN Programmable Flag Timing Offset Registers Mode MBF2 Mail 2 Register IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc. COMMERICAL TEMPERATURE RANGE 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. Port-B Control Logic FWFT CLKB CSB W/RB ENB MBB BE BM SIZE 4678 drw 01 OCTOBER 2008 DSC-4678/5 IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36 ORDERING INFORMATION Device Type Power Speed Package Process/ Temperature Range BLANK Commercial 0oC to +70oC Green Thin Quad Flat Pack TQFP, PK128-1 10 15 Commercial Only Clock Cycle Time tCLK Speed in Nanoseconds Low Power 72V3683 16,384 x 36 3.3V SyncFIFO with Bus-Matching 72V3693 32,768 x 36 3.3V SyncFIFO with Bus-Matching 72V36103 65,536 x 36 3.3V SyncFIFO with Bus-Matching NOTES Industrial temperature range is available by special order. Green parts available. For specific speeds and packages contact your sales office. 4678 drw25 DATASHEET DOCUMENT HISTORY 11/05/2001 pgs. 4-9, 12 and 11/04/2003 05/23/2008 pgs. 1, 6, and 10/22/2008 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support 408-360-1753 email: |
Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT72V3683L15PF8 Datasheet file may be downloaded here without warranties.