IDT72T51248L5BB

IDT72T51248L5BB Datasheet


IDT72T51248 IDT72T51258 IDT72T51268

Part Datasheet
IDT72T51248L5BB IDT72T51248L5BB IDT72T51248L5BB (pdf)
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2.5V MULTI-QUEUE DDR FLOW-CONTROL DEVICES 40 BITS WIDE WITH FIXED 4 QUEUES 8,192 x 40 x 4, 16,384 x 40 x 4 and 32,768 x 40 x 4

IDT72T51248 IDT72T51258 IDT72T51268
• The multi-queue DDR flow-control device contains 4 Queues
each queue has a fixed size of:

IDT72T51248 8,192 x 40 or 16,384 x 20 or 32,768 x 10

IDT72T51258 16,384 x 40 or 32,768 x 20 or 65,536 x 10

IDT72T51268 32,768 x 40 or 65,536 x 20 or 131,072 x 10
• Write to and Read from the same queue or different queues
simultaneously via totally independent ports
• Up to 200MHz operating frequency or 8Gbps throughput in SDR mode
• Up to 100MHz operating frequency or 8Gbps throughput in DDR mode
• User selectable Single Data Rate SDR or Double Data Rate

DDR modes on both the write port and read port
• 100% Bus Utilization, Read and Write on every clock cycle
• Global Bus Matching - All Queues have same Input bus width
and same Output bus width
• User Selectable Bus Matching options:
- x40in to x40out - x40in to x20out
- x40in to x10out
- x20in to x40out - x20in to x20out
- x20in to x10out
- x10in to x40out - x10in to x20out
- x10in to x10out
• All I/O is LVTTL/ HSTL/ eHSTL user selectable
• 3.3V tolerant inputs in LVTTL mode
• ERCLK & EREN Echo outputs on read port
• Write Chip Select WCS input for write port
• Read Chip Select RCS input for read port
• User Selectable IDT Standard mode using EF and FF or FWFT
mode using IR and OR
• All 4 Queues have dedicated flag outputs FF/IR, EF/OR, PAF
and PAE
• A Composite Full/ Input Ready Flag gives status of the queue
selected on the write port
• A Composite Empty/ Output Ready flag gives status of the
queue selected on the read port
• Programmable Almost Empty and Almost Full flags per Queue
• Dedicated Serial Port for flag programming
• A Partial Reset is provided for each queue
• Power Down pin minimizes power consumption
• 2.5V Supply Voltage
• Available in a 324-pin Plastic Ball Grid Array PBGA
19mm x 19mm, 1mm Pitch
• JTAG port provides boundary scan function and optional
programming mode
ORDERING INFORMATION

Device Type

X Power

XX Speed

X Package

Process / Temperature

Range

BLANK I 1

Commercial 0°C to +70°C Industrial -40°C to +85°C

Plastic Ball Grid Array PBGA, BB324-1

Commercial Only

Clock Cycle Time tCLK

Commercial and Industrial Speed in Nanoseconds

Low Power
72T51248 72T51258 72T51268
8,192 x 40 x 4 2.5V Multi-Queue DDR Flow-Control Device 16,384 x 40 x 4 2.5V Multi-Queue DDR Flow-Control Device 32,768 x 40 x 4 2.5V Multi-Queue DDR Flow-Control Device
6159drw45

NOTE Industrial temperature range product for the 6-7ns speed grade is available as a standard device. All other speed grades are available by special order.

DATASHEET DOCUMENT HISTORY
12/01/2003
pgs. 1, 5, 11, and
03/22/2005
pgs. 1, 3, 6, 10-12, and
02/20/2009

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More datasheets: CA3106E22-18SF80 | HE24-1A83-02 | MDM-31PH004A | LE87501NQCT | LE87501NQC | IDT72T51248L6-7BBI | IDT72T51248L6-7BB | IDT72T51258L5BB | IDT72T51258L6-7BB | IDT72T51258L6-7BBI


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Datasheet ID: IDT72T51248L5BB 637356