IDT72T20128L10BB

IDT72T20128L10BB Datasheet

IDT72T2098, IDT72T20108 IDT72T20118, IDT72T20128

Part	Datasheet
IDT72T20128L10BB	IDT72T20128L10BB (pdf)

Related Parts	Information
IDT72T20118L5BB	IDT72T20118L5BB
IDT72T2098L5BB	IDT72T2098L5BB
IDT72T2098L10BB	IDT72T2098L10BB
IDT72T20118L10BB	IDT72T20118L10BB
IDT72T20118L4BB	IDT72T20118L4BB
IDT72T2098L4BB	IDT72T2098L4BB
IDT72T20118L6-7BB	IDT72T20118L6-7BB
IDT72T2098L6-7BB	IDT72T2098L6-7BB

PDF Datasheet Preview
VOLT HIGH-SPEED TeraSync DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION 32,768 x 20/65,536 x 10, 65,536 x 20/131,072 x 10 131,072 x 20/262,144 x 10, 262,144 x 20/524,288 x 10 IDT72T2098, IDT72T20108 IDT72T20118, IDT72T20128 • Choose among the following memory organizations IDT72T2098 32,768 x 20/65,536 x 10 IDT72T20108 65,536 x 20/131,072 x 10 IDT72T20118 131,072 x 20/262,144 x 10 IDT72T20128 262,144 x 20/524,288 x 10 • Up to 250MHz operating frequency or 5Gbps throughput in SDR mode • Up to 110MHz operating frequency or 5Gbps throughput in DDR mode • Users selectable input port to output port data rates, 500Mb/s Data Rate -DDR to DDR -DDR to SDR -SDR to DDR -SDR to SDR • User selectable HSTL or LVTTL I/Os • Read Enable & Read Clock Echo outputs aid high speed operation • 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage • 3.3V Input tolerant • Mark & Retransmit, resets read pointer to user marked position • Write Chip Select WCS input enables/disables Write Operations • Read Chip Select RCS synchronous to RCLK • Programmable Almost-Empty and Almost-Full flags, each flag can default to one of four preselected offsets • Dedicated serial clock input for serial programming of flag offsets • User selectable input and output port bus sizing -x20 in to x20 out -x20 in to x10 out -x10 in to x20 out -x10 in to x10 out • Auto power down minimizes standby power consumption • Master Reset clears entire FIFO • Partial Reset clears data, but retains programmable settings • Empty and Full flags signal FIFO status • Select IDT Standard timing using EF and FF flags or First Word Fall Through timing using OR and IR flags • Output enable puts data outputs into High-Impedance state • JTAG port, provided for Boundary Scan function • 208 Ball Grid array PBGA , 17mm x 17mm, 1mm pitch • Easily expandable in depth and width • Independent Read and Write Clocks permit reading and writing simultaneously • High-performance submicron CMOS technology • Industrial temperature range -40°C to +85°C is available • Green parts available, see ordering information FUNCTIONAL BLOCK DIAGRAM WEN WCLK D0 -Dn x20, x10 SREN SEN SCLK WCS WSDR INPUT REGISTER OFFSET REGISTER WRITE CONTROL LOGIC WRITE POINTER RAM ARRAY 32,768 x 20 or 65,536 x 10 65,536 x 20 or 131,072 x 10 131,072 x 20 or 262,144 x 10 262,144 x 20 or 524,288 x 10 FLAG LOGIC READ POINTER FF/IR PAF EF/OR PAE FWFT FSEL0 FSEL1 IW OW MRS PRS TCK TRST TMS TDO BUS CONFIGURATION RESET LOGIC JTAG CONTROL BOUNDARY SCAN OUTPUT REGISTER READ CONTROL LOGIC Vref HSTL HSTL I/0 CONTROL OE Q0 -Qn x20, x10 EREN ERCLK IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. RT MARK RSDR RCLK REN RCS 5996 drw01 FEBRUARY 2009 DSC-5996/11 IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN CONFIGURATIONS A1 BALL PAD CORNER VCC DNC ORDERING INFORMATION Device Type X Power XX Speed X Package Process / Temperature Range BLANK I 1 Commercial 0°C to +70°C Industrial -40°C to +85°C Green Plastic Ball Grid Array PBGA, BB208-1 Commercial Only Commercial Only Clock Cycle Time tCLK Commercial and Industrial Speed in Nanoseconds Commercial Only Low Power 72T2098 72T20108 72T20118 72T20128 32,768 x 20/65,536 x 10 2.5V High-Speed TeraSyncTM DDR/SDR FIFO 65,536 x 20/131,072 x 10 2.5V High-Speed TeraSyncTM DDR/SDR FIFO 131,072 x 20/262,144 x 10 2.5V High-Speed TeraSyncTM DDR/SDR FIFO 262,144 x 20/524,288 x 10 2.5V High-Speed TeraSyncTM DDR/SDR FIFO 5996 drw36 Industrial temperature range product for the 6-7ns speed grade is available as a standard device. All other speed grades are available by special order. Green parts are available. For specific speeds and packages contact your sales office. DATASHEET DOCUMENT HISTORY 03/01/2002 pgs. 1, 4, 6, 8, 9, and 04/08/2002 pgs. 1, 8, 9, 11, 32-35, 41, 45-47, and 04/24/2002 pgs. 19, and 05/24/2002 pgs. 2, 6-9, and 11/21/2002 pgs. 1, and 02/11/2003 pgs. 7, 8, and 03/20/2003 pgs. 24, 26, 27, and 12/17/2003 pgs. 10, 30-33, 35-37, 43, and 09/21/2004 pgs. 1, 3, 9-11, 17, and 02/13/2009 pgs. 1 and CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support 408-360-1753 email:

PDF Datasheet Preview

VOLT HIGH-SPEED TeraSync DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
32,768 x 20/65,536 x 10, 65,536 x 20/131,072 x 10 131,072 x 20/262,144 x 10, 262,144 x 20/524,288 x 10

IDT72T2098, IDT72T20108 IDT72T20118, IDT72T20128
• Choose among the following memory organizations IDT72T2098 32,768 x 20/65,536 x 10 IDT72T20108 65,536 x 20/131,072 x 10 IDT72T20118 131,072 x 20/262,144 x 10 IDT72T20128 262,144 x 20/524,288 x 10
• Up to 250MHz operating frequency or 5Gbps throughput in SDR mode
• Up to 110MHz operating frequency or 5Gbps throughput in DDR mode
• Users selectable input port to output port data rates, 500Mb/s

Data Rate -DDR to DDR -DDR to SDR -SDR to DDR -SDR to SDR
• User selectable HSTL or LVTTL I/Os
• Read Enable & Read Clock Echo outputs aid high speed operation
• 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
• 3.3V Input tolerant
• Mark & Retransmit, resets read pointer to user marked position
• Write Chip Select WCS input enables/disables Write Operations
• Read Chip Select RCS synchronous to RCLK
• Programmable Almost-Empty and Almost-Full flags, each flag
can default to one of four preselected offsets
• Dedicated serial clock input for serial programming of flag offsets
• User selectable input and output port bus sizing
-x20 in to x20 out -x20 in to x10 out -x10 in to x20 out -x10 in to x10 out
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty and Full flags signal FIFO status
• Select IDT Standard timing using EF and FF flags or First Word Fall Through timing using OR and IR flags
• Output enable puts data outputs into High-Impedance state
• JTAG port, provided for Boundary Scan function
• 208 Ball Grid array PBGA , 17mm x 17mm, 1mm pitch
• Easily expandable in depth and width
• Independent Read and Write Clocks permit reading and writing simultaneously
• High-performance submicron CMOS technology
• Industrial temperature range -40°C to +85°C is available
• Green parts available, see ordering information

FUNCTIONAL BLOCK DIAGRAM

WEN WCLK

D0 -Dn x20, x10

SREN SEN SCLK

WCS WSDR

INPUT REGISTER

OFFSET REGISTER

WRITE CONTROL LOGIC

WRITE POINTER

RAM ARRAY 32,768 x 20 or 65,536 x 10 65,536 x 20 or 131,072 x 10 131,072 x 20 or 262,144 x 10 262,144 x 20 or 524,288 x 10

FLAG LOGIC

READ POINTER

FF/IR PAF EF/OR PAE

FWFT FSEL0 FSEL1

IW OW

MRS PRS

TCK TRST TMS TDO

BUS CONFIGURATION

RESET LOGIC

JTAG CONTROL BOUNDARY SCAN

OUTPUT REGISTER

READ CONTROL

LOGIC

Vref HSTL

HSTL I/0 CONTROL

OE Q0 -Qn x20, x10

EREN ERCLK

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.

RT MARK RSDR

RCLK REN RCS
5996 drw01

FEBRUARY 2009

DSC-5996/11

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS 32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

A1 BALL PAD CORNER

VCC DNC
ORDERING INFORMATION

Device Type

X Power

XX Speed

X Package

Process /

Temperature

Range

BLANK I 1

Commercial 0°C to +70°C Industrial -40°C to +85°C Green

Plastic Ball Grid Array PBGA, BB208-1

Commercial Only

Commercial Only

Clock Cycle Time tCLK

Commercial and Industrial Speed in Nanoseconds

Commercial Only

Low Power
72T2098 72T20108 72T20118 72T20128
32,768 x 20/65,536 x 10 2.5V High-Speed TeraSyncTM DDR/SDR FIFO 65,536 x 20/131,072 x 10 2.5V High-Speed TeraSyncTM DDR/SDR FIFO 131,072 x 20/262,144 x 10 2.5V High-Speed TeraSyncTM DDR/SDR FIFO 262,144 x 20/524,288 x 10 2.5V High-Speed TeraSyncTM DDR/SDR FIFO
5996 drw36

Industrial temperature range product for the 6-7ns speed grade is available as a standard device. All other speed grades are available by special order.

Green parts are available. For specific speeds and packages contact your sales office.

DATASHEET DOCUMENT HISTORY
03/01/2002 pgs. 1, 4, 6, 8, 9, and 04/08/2002 pgs. 1, 8, 9, 11, 32-35, 41, 45-47, and 04/24/2002 pgs. 19, and 05/24/2002 pgs. 2, 6-9, and 11/21/2002 pgs. 1, and 02/11/2003 pgs. 7, 8, and 03/20/2003 pgs. 24, 26, 27, and 12/17/2003 pgs. 10, 30-33, 35-37, 43, and 09/21/2004 pgs. 1, 3, 9-11, 17, and 02/13/2009 pgs. 1 and

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775
for Tech Support 408-360-1753
email:

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT72T20128L10BB Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT72T20128L10BB 637354