IDT72P51777L6BB

IDT72P51777L6BB Datasheet

IDT72P51767 IDT72P51777

Part	Datasheet
IDT72P51777L6BB	IDT72P51777L6BB (pdf)

Related Parts	Information
IDT72P51767L6BB	IDT72P51767L6BB
IDT72P51767L7-5BBI	IDT72P51767L7-5BBI
IDT72P51767L7-5BB	IDT72P51767L7-5BB
IDT72P51777L7-5BBI	IDT72P51777L7-5BBI
IDT72P51777L7-5BB	IDT72P51777L7-5BB

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1.8V MULTI-QUEUE FLOW-CONTROL DEVICES 128 QUEUES 40 BIT WIDE CONFIGURATION 5,242,880 bits 10,485,760 bits IDT72P51767 IDT72P51777 • Choose from among the following memory density options IDT72P51767 Total Available Memory = 5,242,880 bits IDT72P51777 Total Available Memory = 10,485,760 bits • Configurable from 1 to 128 Queues • Multiple default configurations of symmetrical queues • Default multi-queue device configurations IDT72P51767 512 x 40 x 128Q IDT72P51777 1,024 x 40 x 128Q • Number of queues and queue sizes may be configured at master reset, though serial programming, via the queue address bus • 166 MHz High speed operation 6ns cycle time • 0.48ns access time • Independent Read and Write access per queue • Echo Read Clock available • Internal PLL • On-chip Output Impedance matching FUNCTIONAL BLOCK DIAGRAM • User Selectable Bus Matching Options x40 in to x40 out x20 in to x20 out x40 in to x20 out x20in to x40out • User selectable I/O 1.5V HSTL or 1.8V eHSTL • 100% Bus Utilization, Read and Write on every clock cycle • Selectable Back off one BOI or IDT standard mode of operation • Ability to operate on packet or word boundaries • Mark and Re-Write operation • Mark and Re-Read operation • Individual, Active queue flags EF, FF, PAE, PAF • 8 bit parallel flag status on both read and write ports • Direct or polled operation of flag status bus • Expansion of up to 256 queues • JTAG Functionality Boundary Scan • Available in a 376-pin BGA, 1mm pitch, 23mm x 23mm • HIGH Performance submicron CMOS technology • Industrial temperature range -40°C to +85°C is available • Green parts available, seeing Ordering Information WADEN FSTR WRADD 8 WEN WCLK Din x40 or x20 DATA IN WRITE CONTROL 10G DDR MULTI-QUEUE FLOW-CONTROL DEVICE Q127 Q126 Q125 READ CONTROL ECHO CLOCK 2 RADEN ESTR RDADD 8 REN RCLK EREN Qout x40 or x20 DATA OUT READ FLAGS PAFn EF PAE PAEn 8 WRITE FLAGS IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. 6724 drw01 FEBRUARY 2009 DSC-6724/2 IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES 128 QUEUES 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Table of Contents Features 1 Description 5 Pin configuration 7 Detailed Description 8 Pin Descriptions 10 Pin number table 15 Recommended DC operating conditions 16 Absolute maximum ratings 16 DC electrical characteristics 17 AC electrical characteristics 19 Functional description 22 Serial Programming 24 Default Programming 27 Parallel Programming 27 Modes of operation 29 Standard mode operation 29 IDT Standard mode vs. BOI mode 29 PLL on vs PLL off modes 30 Read Queue Selection and Read Operation 33 Switching Queues on the Write Port 34 Switching Queues on the Read Port 44 Flag Description 52 PAFn Flag Bus Operation 52 Full Flag Operation 52 Empty Flag Operation 52 Almost Full Flag 53 Almost Empty Flag 53 JTAG Interface 83 JTAGAC electrical characteristics 87 Ordering Information 88 List of Tables Table 1 Summary of the differences between the 4M MQ and 10G MQ 9 Table 2 DC and AC specifications informative 21 Table 3 IDT to XGMII Interface Mapping Schema 21 Table 4 Device programming mode comparison 22 Table 5 Setting the queue programming mode during master reset 23 Table 6 ID[2:0] and WRADD[7:5]/RDADD[7:5] Configuration 27 Table 7 Parallel Programming Mode Queue Configuration Example 1 28 Table 8 Write Address Bus, WRADD[7:0] 32 Table 9 Read Address Bus, RDADD[7:0] 33 Table 10 Write Queue Switch Operation 35 Table 11 Backup Usage when Re-entering a Queue 43 Table 13 Same Queue Switch 45 Table 12 Read Queue Switch Operation 45 Table 14 Flag operation boundaries & Timing 55 Table 15 Interface Data Rates 57 Table 16 Bus-Matching Configurations 58 FEBRUARY 11, 2009 IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES 128 QUEUES 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES List of Figures Figure Multi-Queue Flow-Control Device Block Diagram 6 Figure 2a. AC Test Load 18 Figure 2b. Lumped Capacitive Load, Typical Derating 18 Figure HSTL Termination for XGMII 21 Figure Reference Signals 22 Figure Expansion for Unlimited Number of Multi-Queue Devices Example 28 Figure Device Programming Hierarchy 29 Figure DDR Read Operation with PLL ON 30 Figure DDR Read Operation with PLL OFF 30 Figure SDR Read Operation with PLL ON 31 Figure SDR Read Operation with PLL OFF 31 Figure Write Port Switching Queues Signal Sequence 34 Figure Switching Queues Bus Efficiency 34 Figure Simultaneous Queue Switching 35 Figure Application Reading words from the MQ using the EOP bit to end the read operation 36 Figure Output Data during a Queue Switch SDR w/o PLL 37 Figure Output Data during a Queue Switch SDR w/ PLL 38 Figure Output Data during a Queue Switch DDR w/ PLL 39 Figure Output Data during a Queue Switch DDR w/o PLL 40 Figure Output Data during two Queue Switches DDR w/ PLL 41 Figure Output Data during two Queue Switches DDR w/o PLL 42 Figure Read Port Switching Queues Signal Sequence 44 Figure Switching Queues Bus Efficiency 44 Figure Simultaneous Queue Switching 45 Figure MARK and Re-Write Sequence 46 Figure MARK and Re-Read Sequence 46 Figure MARKing a Queue - Write Queue MARK 47 Figure MARKing a Queue - Read Queue MARK 47 Figure UN-MARKing a Queue - Write Queue UN-MARK 48 Figure UN-MARKing a Queue - Read Queue UN-MARK 48 Figure Leaving a MARK active on the Write Port 49 Figure Leaving a MARK active on the Read Port 49 Figure Inactivating a MARK on the Write Port Active 50 Figure Inactivating a MARK on the Read Port Active 50 Figure DDR Source Synchronous Center Aligned Clocking 57 Figure SDR Edge Aligned Clocking 57 Figure Bus-Matching Byte Arrangement 59 Figure Master Reset 60 Figure Default Programming 61 Figure Write Address/Read Address Programming 62 Figure Serial Port Connection for Serial Programming 63 Figure Serial Programming 2 Device Expansion 64 Figure SDR Write Queue Select, Write Operation and Full Flag Operation 65 Figure DDR Write Operation, Write Queue Select, Full Flag Operation 66 Figure Write Queue Select, Mark and Rewrite 67 Figure Full Flag Timing in Expansion Configuration 68 Figure SDR Read Queue Select, Read Operation IDT mode 69 Figure DDR Read Operation, Read Queue Select, EF & PAE Flag Operation 70 Figure Read Queue Select, Mark and Reread IDT mode 71 Figure Standard Mode Pointers on Queue Re-entry for DDR Read Operation 72 Figure BOI Mode Pointers on Queue Re-entry for DDR Read Operation 72 Figure Read Queue Selection with Read Operations IDT mode SDR mode, PLL = OFF 73 Figure Read Queue Select, Read Operation and OE Timing 74 Figure Almost Full Flag Timing and Queue Switch 75 Figure Almost Full Flag Timing 75 FEBRUARY 11, 2009 IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES 128 QUEUES 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES List of Figures Continued Figure Almost Empty Flag Timing 76 Figure PAEn - Direct Mode - Status Word Selection 77 Figure PAFn - Direct Mode - Status Word Selection 77 Figure PAEn - Direct Mode, Flag Operation 78 Figure PAFn - Direct Mode, Flag Operation 79 Figure PAFn Bus - Polled Mode 80 Figure Connecting two 10G MQ 128Q devices in Expansion Mode 81 Figure Connecting THREE or more 10G MQ 128Q in Expansion Mode Using WADDR bit 7/RDADD bit 7 82 Figure Boundary Scan Architecture 83 Figure TAP Controller State Diagram 84 Figure Standard JTAG Timing 87 FEBRUARY 11, 2009 IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES 128 QUEUES 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES The IDT72P51767/ IDT72P51777 multi-queue flow-control devices are single chip solutions containing up to 128 configurable queues. All queues within the device have a common data input bus, Din [39:0] write port and a common data output bus Qout [39:0], read port . Data written into the write port is directed to a respective queue via an integrated de-multiplex function. Data read from the read port is accessed from a given queue transparently via an internal multiplex operation. Data writes and reads can be performed at high speeds up to 166MHz DDR allowing data rates up to 10Gigabits/s OC-192 . By utilizing high speed interfaces such as 1.5V HSTL, coupled with a x40 bit data bus and 10Mb of data storage, the 10G Multi-Queue can interface with the industry standard 10 Gigabits/sec Media Independent Interface XGMII to allow high speed data transmission over 10G Ethernet and SONET line cards. Data write and read operations are totally independent of each other. The Write Clock and Read Clock can operate at independent frequencies. A different queue may be selected on the write port and read port or both ports may select the same queue simultaneously. Multiple clocking schemes are offered for this device as well. The user can utilize either single ended or differential clocking for DDR read operations. DDR write operation utilize a single ended clock. SDR write and read operations utilize a single ended clock. The devices provide Full flag and Empty flag status for the queue selected for write and read operations respectively. Also a Programmable Almost Full PAF and Programmable Almost Empty PAE flag for each queue is provided. Two 8 bit programmable flag busses PAFn, PAEn are available, providing status of queues that are not the present queue selected for write or read operations. When 8 or fewer queues are configured in the device, these flag busses provide an individual flag per queue, when more than 8 queues are used the queue status is multiplexed through the 8 stus lines. The multiplexing can be configured either a Polled or Direct mode of bus. Bus Matching is available on this device either port can be x20 bits or x40 bits wide. When Bus Matching is used the device ensures the logical transfer of data throughput. With a 40 data bits configuration parity checking and packet tagging is achievable if desired. Parity checking is available through the use of 4 user selectable bits as part of the 40 bit word. The user will be able to pass along parity bits through the Multi-Queue to use for error detection in a up/down stream device. The Multi-Queue device does not provide parity checking circuits. In Back off One mode, the user can switch queues without having to read the last pipelined data word that is stored in the output register which in IDT standard mode is required to be read out during a queue switch The last pipelined data word in BOI mode is retained in the output data register until it is actively read. A Mark and Re-write and a Mark and Re-read function are available on the write and read ports respectively. These functions allows for a mark location to be independently issued on the read and/or write ports, in their respective queues. The option to reset a given queue to the mark location effectively dropping data written into the queue or allow data to be read again from the device. The devices offer a default configuration upon reset, offering 128 symmetrical queues configured at start-up, which means the user can program the number of queues to divide the 10Mb/5Mb of memory depending on the device. The Multi-Queues can even be programmed to support one single queue to be used as a FIFO for high performance applications of sequential queuing. The programmable flag positions are also user programmable. If the user does not wish to program the multi-queue device, a default option is available that configures the device in a predetermined manner. A Master Reset latches in all configuration setup pins and must be performed before programming of the device can take place. The multi-queue flow-control devices have the capability of operating its I/O in either 1.5V HSTL , or 1.8V eHSTL mode. The type of I/O is selected via the IOSEL input. The core supply voltage VCC to the multi-queue is always 1.8V, however the output levels can be set independently via a separate supply, VDDQ. The package used will be a 23mm x 23mm, BB-376 BGA package for better noise immunity and ground bounce prevention. A JTAG test port is provided, here the multi-queue flow-control device has a fully functional Boundary Scan feature, compliant with IEEE Standard Test Access Port and Boundary Scan Architecture. FEBRUARY 11, 2009 IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES 128 QUEUES 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits WCLK WEN WCS x20, x40 D0 - D39 INPUT DEMUX 8 WRADD WADEN Write Control Logic Write Pointers FSTR PAFn FSYNC ORDERING INFORMATION Device Type X Power XX Speed Package Process / Temperature Range BLANK I 1 Commercial 0°C to +70°C Industrial -40°C to +85°C Green Ball Grid Array BGA, BB376-1 Commercial Only Clock Cycle Time tCLK Commercial and Industrial Speed in Nanoseconds Low Power 72P51767 5,898,240 bits 10G DDR Multi-Queue Flow-Control Device 1.8V 72P51777 11,796,480 bits 10G DDR Multi-Queue Flow-Control Device 1.8V 6724 drw79 NOTES Industrial temperature range product for the 7-5ns is available as a standard device. All other speed grades available by special order. Green parts are available. For specific speeds contact your local sales office. DATASHEET DOCUMENT HISTORY 01/18/2006 pgs. 1, 17, 19, 20, 30, and 02/11/2009 pg. CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support 408-360-1533 email:

PDF Datasheet Preview

1.8V MULTI-QUEUE FLOW-CONTROL DEVICES 128 QUEUES 40 BIT WIDE CONFIGURATION
5,242,880 bits 10,485,760 bits

IDT72P51767 IDT72P51777
• Choose from among the following memory density options IDT72P51767 Total Available Memory = 5,242,880 bits IDT72P51777 Total Available Memory = 10,485,760 bits
• Configurable from 1 to 128 Queues
• Multiple default configurations of symmetrical queues
• Default multi-queue device configurations

IDT72P51767 512 x 40 x 128Q IDT72P51777 1,024 x 40 x 128Q
• Number of queues and queue sizes may be configured at master reset, though serial programming, via the queue address bus
• 166 MHz High speed operation 6ns cycle time
• 0.48ns access time
• Independent Read and Write access per queue
• Echo Read Clock available
• Internal PLL
• On-chip Output Impedance matching

FUNCTIONAL BLOCK DIAGRAM
• User Selectable Bus Matching Options x40 in to x40 out x20 in to x20 out x40 in to x20 out x20in to x40out
• User selectable I/O 1.5V HSTL or 1.8V eHSTL
• 100% Bus Utilization, Read and Write on every clock cycle
• Selectable Back off one BOI or IDT standard mode of operation
• Ability to operate on packet or word boundaries
• Mark and Re-Write operation
• Mark and Re-Read operation
• Individual, Active queue flags EF, FF, PAE, PAF
• 8 bit parallel flag status on both read and write ports
• Direct or polled operation of flag status bus
• Expansion of up to 256 queues
• JTAG Functionality Boundary Scan
• Available in a 376-pin BGA, 1mm pitch, 23mm x 23mm
• HIGH Performance submicron CMOS technology
• Industrial temperature range -40°C to +85°C is available
• Green parts available, seeing Ordering Information

WADEN FSTR WRADD
8 WEN WCLK

Din x40 or x20

DATA IN

WRITE CONTROL
10G DDR MULTI-QUEUE FLOW-CONTROL DEVICE Q127 Q126 Q125

READ CONTROL

ECHO CLOCK 2 RADEN ESTR RDADD 8 REN RCLK EREN

Qout x40 or x20 DATA OUT

READ FLAGS

PAFn

EF PAE

PAEn 8

WRITE FLAGS

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
6724 drw01

FEBRUARY 2009

DSC-6724/2

IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES 128 QUEUES 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

Table of Contents

Features 1 Description 5 Pin configuration 7 Detailed Description 8 Pin Descriptions 10 Pin number table 15 Recommended DC operating conditions 16 Absolute maximum ratings 16 DC electrical characteristics 17 AC electrical characteristics 19 Functional description 22
Serial Programming 24 Default Programming 27 Parallel Programming 27 Modes of operation 29 Standard mode operation 29 IDT Standard mode vs. BOI mode 29 PLL on vs PLL off modes 30 Read Queue Selection and Read Operation 33 Switching Queues on the Write Port 34 Switching Queues on the Read Port 44 Flag Description 52 PAFn Flag Bus Operation 52 Full Flag Operation 52 Empty Flag Operation 52 Almost Full Flag 53 Almost Empty Flag 53 JTAG Interface 83 JTAGAC electrical characteristics 87 Ordering Information 88

List of Tables

Table 1 Summary of the differences between the 4M MQ and 10G MQ 9 Table 2 DC and AC specifications informative 21 Table 3 IDT to XGMII Interface Mapping Schema 21 Table 4 Device programming mode comparison 22 Table 5 Setting the queue programming mode during master reset 23 Table 6 ID[2:0] and WRADD[7:5]/RDADD[7:5] Configuration 27 Table 7 Parallel Programming Mode Queue Configuration Example 1 28 Table 8 Write Address Bus, WRADD[7:0] 32 Table 9 Read Address Bus, RDADD[7:0] 33 Table 10 Write Queue Switch Operation 35 Table 11 Backup Usage when Re-entering a Queue 43 Table 13 Same Queue Switch 45 Table 12 Read Queue Switch Operation 45 Table 14 Flag operation boundaries & Timing 55 Table 15 Interface Data Rates 57 Table 16 Bus-Matching Configurations 58

FEBRUARY 11, 2009

IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES 128 QUEUES 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

List of Figures

Figure Multi-Queue Flow-Control Device Block Diagram 6 Figure 2a. AC Test Load 18 Figure 2b. Lumped Capacitive Load, Typical Derating 18 Figure HSTL Termination for XGMII 21 Figure Reference Signals 22 Figure Expansion for Unlimited Number of Multi-Queue Devices Example 28 Figure Device Programming Hierarchy 29 Figure DDR Read Operation with PLL ON 30 Figure DDR Read Operation with PLL OFF 30 Figure SDR Read Operation with PLL ON 31 Figure SDR Read Operation with PLL OFF 31 Figure Write Port Switching Queues Signal Sequence 34 Figure Switching Queues Bus Efficiency 34 Figure Simultaneous Queue Switching 35 Figure Application Reading words from the MQ using the EOP bit to end the read operation 36 Figure Output Data during a Queue Switch SDR w/o PLL 37 Figure Output Data during a Queue Switch SDR w/ PLL 38 Figure Output Data during a Queue Switch DDR w/ PLL 39 Figure Output Data during a Queue Switch DDR w/o PLL 40 Figure Output Data during two Queue Switches DDR w/ PLL 41 Figure Output Data during two Queue Switches DDR w/o PLL 42 Figure Read Port Switching Queues Signal Sequence 44 Figure Switching Queues Bus Efficiency 44 Figure Simultaneous Queue Switching 45 Figure MARK and Re-Write Sequence 46 Figure MARK and Re-Read Sequence 46 Figure MARKing a Queue - Write Queue MARK 47 Figure MARKing a Queue - Read Queue MARK 47 Figure UN-MARKing a Queue - Write Queue UN-MARK 48 Figure UN-MARKing a Queue - Read Queue UN-MARK 48 Figure Leaving a MARK active on the Write Port 49 Figure Leaving a MARK active on the Read Port 49 Figure Inactivating a MARK on the Write Port Active 50 Figure Inactivating a MARK on the Read Port Active 50 Figure DDR Source Synchronous Center Aligned Clocking 57 Figure SDR Edge Aligned Clocking 57 Figure Bus-Matching Byte Arrangement 59 Figure Master Reset 60 Figure Default Programming 61 Figure Write Address/Read Address Programming 62 Figure Serial Port Connection for Serial Programming 63 Figure Serial Programming 2 Device Expansion 64 Figure SDR Write Queue Select, Write Operation and Full Flag Operation 65 Figure DDR Write Operation, Write Queue Select, Full Flag Operation 66 Figure Write Queue Select, Mark and Rewrite 67 Figure Full Flag Timing in Expansion Configuration 68 Figure SDR Read Queue Select, Read Operation IDT mode 69 Figure DDR Read Operation, Read Queue Select, EF & PAE Flag Operation 70 Figure Read Queue Select, Mark and Reread IDT mode 71 Figure Standard Mode Pointers on Queue Re-entry for DDR Read Operation 72 Figure BOI Mode Pointers on Queue Re-entry for DDR Read Operation 72 Figure Read Queue Selection with Read Operations IDT mode SDR mode, PLL = OFF 73 Figure Read Queue Select, Read Operation and OE Timing 74 Figure Almost Full Flag Timing and Queue Switch 75 Figure Almost Full Flag Timing 75

FEBRUARY 11, 2009

IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES 128 QUEUES 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

List of Figures Continued

Figure Almost Empty Flag Timing 76 Figure PAEn - Direct Mode - Status Word Selection 77 Figure PAFn - Direct Mode - Status Word Selection 77 Figure PAEn - Direct Mode, Flag Operation 78 Figure PAFn - Direct Mode, Flag Operation 79 Figure PAFn Bus - Polled Mode 80

Figure Connecting two 10G MQ 128Q devices in Expansion Mode 81

Figure Connecting THREE or more 10G MQ 128Q in Expansion Mode Using WADDR bit 7/RDADD bit 7 82

Figure Boundary Scan Architecture 83

Figure TAP Controller State Diagram 84

Figure Standard JTAG Timing 87

FEBRUARY 11, 2009

IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES 128 QUEUES 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

The IDT72P51767/ IDT72P51777 multi-queue flow-control devices are single chip solutions containing up to 128 configurable queues. All queues within the device have a common data input bus, Din [39:0] write port and a common data output bus Qout [39:0], read port . Data written into the write port is directed to a respective queue via an integrated de-multiplex function. Data read from the read port is accessed from a given queue transparently via an internal multiplex operation. Data writes and reads can be performed at high speeds up to 166MHz DDR allowing data rates up to 10Gigabits/s OC-192 . By utilizing high speed interfaces such as 1.5V HSTL, coupled with a x40 bit data bus and 10Mb of data storage, the 10G Multi-Queue can interface with the industry standard 10 Gigabits/sec Media Independent Interface XGMII to allow high speed data transmission over 10G Ethernet and SONET line cards. Data write and read operations are totally independent of each other. The Write Clock and Read Clock can operate at independent frequencies. A different queue may be selected on the write port and read port or both ports may select the same queue simultaneously. Multiple clocking schemes are offered for this device as well. The user can utilize either single ended or differential clocking for DDR read operations. DDR write operation utilize a single ended clock. SDR write and read operations utilize a single ended clock.

The devices provide Full flag and Empty flag status for the queue selected for write and read operations respectively. Also a Programmable Almost Full PAF and Programmable Almost Empty PAE flag for each queue is provided. Two 8 bit programmable flag busses PAFn, PAEn are available, providing status of queues that are not the present queue selected for write or read operations. When 8 or fewer queues are configured in the device, these flag busses provide an individual flag per queue, when more than 8 queues are used the queue status is multiplexed through the 8 stus lines. The multiplexing can be configured either a Polled or Direct mode of bus.

Bus Matching is available on this device either port can be x20 bits or x40 bits wide. When Bus Matching is used the device ensures the logical transfer of data throughput. With a 40 data bits configuration parity checking and packet tagging is achievable if desired. Parity checking is available through the use of
4 user selectable bits as part of the 40 bit word. The user will be able to pass along parity bits through the Multi-Queue to use for error detection in a up/down stream device. The Multi-Queue device does not provide parity checking circuits.

In Back off One mode, the user can switch queues without having to read the last pipelined data word that is stored in the output register which in IDT standard mode is required to be read out during a queue switch The last pipelined data word in BOI mode is retained in the output data register until it is actively read.

A Mark and Re-write and a Mark and Re-read function are available on the write and read ports respectively. These functions allows for a mark location to be independently issued on the read and/or write ports, in their respective queues. The option to reset a given queue to the mark location effectively dropping data written into the queue or allow data to be read again from the device.

The devices offer a default configuration upon reset, offering 128 symmetrical queues configured at start-up, which means the user can program the number of queues to divide the 10Mb/5Mb of memory depending on the device. The Multi-Queues can even be programmed to support one single queue to be used as a FIFO for high performance applications of sequential queuing. The programmable flag positions are also user programmable. If the user does not wish to program the multi-queue device, a default option is available that configures the device in a predetermined manner. A Master Reset latches in all configuration setup pins and must be performed before programming of the device can take place.

The multi-queue flow-control devices have the capability of operating its I/O in either 1.5V HSTL , or 1.8V eHSTL mode. The type of I/O is selected via the IOSEL input. The core supply voltage VCC to the multi-queue is always 1.8V, however the output levels can be set independently via a separate supply, VDDQ. The package used will be a 23mm x 23mm, BB-376 BGA package for better noise immunity and ground bounce prevention.

A JTAG test port is provided, here the multi-queue flow-control device has a fully functional Boundary Scan feature, compliant with IEEE Standard Test Access Port and Boundary Scan Architecture.

FEBRUARY 11, 2009

IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES 128 QUEUES 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits

WCLK WEN WCS
x20, x40

D0 - D39

INPUT DEMUX
8 WRADD WADEN

Write Control Logic

Write Pointers

FSTR PAFn

FSYNC
ORDERING INFORMATION

Device Type

X Power

XX Speed

Package

Process / Temperature

Range

BLANK I 1

Commercial 0°C to +70°C Industrial -40°C to +85°C

Green

Ball Grid Array BGA, BB376-1

Commercial Only

Clock Cycle Time tCLK

Commercial and Industrial Speed in Nanoseconds

Low Power
72P51767 5,898,240 bits 10G DDR Multi-Queue Flow-Control Device 1.8V 72P51777 11,796,480 bits 10G DDR Multi-Queue Flow-Control Device 1.8V
6724 drw79

NOTES Industrial temperature range product for the 7-5ns is available as a standard device. All other speed grades available by special order. Green parts are available. For specific speeds contact your local sales office.

DATASHEET DOCUMENT HISTORY
01/18/2006 pgs. 1, 17, 19, 20, 30, and 02/11/2009 pg.

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775
for Tech Support 408-360-1533
email:

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT72P51777L6BB Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT72P51777L6BB 637352