72841L15PFG

72841L15PFG Datasheet

IDT72801 IDT72811 IDT72821 IDT72831 IDT72841 IDT72851

Part	Datasheet
72841L15PFG	72841L15PFG (pdf)

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DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL 1,024 x 9, DUAL 2,048 x 9, DUAL 4,096 x 9, DUAL 8,192 x 9 IDT72801 IDT72811 IDT72821 IDT72831 IDT72841 IDT72851 .EATURES: • The IDT72801 is equivalent to two IDT72201 256 x 9 FIFOs • The IDT72811 is equivalent to two IDT72211 512 x 9 FIFOs • The IDT72821 is equivalent to two IDT72221 1,024 x 9 FIFOs • The IDT72831 is equivalent to two IDT72231 2,048 x 9 FIFOs • The IDT72841 is equivalent to two IDT72241 4,096 x 9 FIFOs • The IDT72851 is equivalent to two IDT72251 8,192 x 9 FIFOs • Offers optimal combination of large capacity, high speed, design flexibility and small footprint • Ideal for prioritization, bidirectional, and width expansion applications • 10 ns read/write cycle time for the IDT72801/72811/72821/72831/ 72841 excluding the IDT72851 • 15 ns read/write cycle time for the IDT72851 • Separate control lines and data lines for each FIFO • Separate Empty, Full, Programmable Almost-Empty and Almost- Full flags for each FIFO • Enable puts output data lines in high-impedance state • Space-saving 64-pin Thin Quad Flat Pack TQFP and Slim Thin Quad Flatpack STQFP • Industrial temperature range to +85°C is available DESCRIPTION: The IDT72801/72811/72821/72831/72841/72851 are dual synchronous clocked FIFOs. The device is functionally equivalent to two IDT72201/72211/ 72221/72231/72241/72251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs designated FIFO A and FIFO B contained in the IDT72801/72811/72821/72831/72841/72851 has a 9-bit input data port DA0 - DA8, DB0 - DB8 and a 9-bit output data port QA0 - QA8, QB0 - QB8 . Each input port is controlled by a free-running clock WCLKA, WCLKB , and two Write Enable pins WENA1, WENA2, WENB1, WENB2 . Data is written into each of the two arrays on every rising clock edge of the Write Clock WCLKA, WCLKB when the appropriate write enable pins are asserted. The output port of each FIFO bank is controlled by its associated clock pin RCLKA, RCLKB and two Read Enable pins RENA1, RENA2, RENB1, RENB2 . The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. An Output Enable pin OEA, OEB is provided on the read port of each FIFO for three-state output control. Each of the two FIFOs has two fixed flags, Empty EFA, EFB and Full FFA, FFB . Two programmable flags, Almost-Empty PAEA, PAEB and Almost-Full PAFA, PAFB , are provided for each FIFO bank to improve memory utilization. If not programmed, the programmable flags default to empty+7 for PAEA and PAEB, and full-7 for PAFA and PAFB. The IDT72801/72811/72821/72831/72841/72851 architecture lends itself to many flexible configurations such as: • 2-level priority data buffering • Bidirectional operation • Width expansion • Depth expansion These FIFOs is fabricated using IDT's high-performance submicron CMOS technology. .UNCTIONAL BLOCK DIAGRAM WCLKA WENA1 WENA2 DA0 - DA8 PAEA WCLKB PAFA FFA WENB1 WENB2 DB0 - DB8 WRITE CONTROL LOGIC WRITE POINTER INPUT REGISTER ORDERING IN.ORMATION IDT Device Type X Power XX Speed XX Package Process/ Temperature Range BLANK I 1 Commercial 0 C to +70 C Industrial -40 C to +85 C Thin Quad Flatpack TQFP, PN64-1 Slim Thin Quad Flatpack STQFP, PP64-1 Commercial Only Clock Cycle Time Commercial and Industrial tCLK , Speed in Commercial and Industrial Nanoseconds 72801 72811 72821 72831 72841 72851 Low Power 256 x 9 Dual SyncFIFO 512 x 9 Dual SyncFIFO 1,024 x 9 Dual SyncFIFO 2,048 x 9 Dual SyncFIFO 4,096 x 9 Dual SyncFIFO 8,192 x 9 Dual SyncFIFO NOTES Industrial temperature range product for 15ns and 25ns speed grade are available as a standard device. 3034 drw 19 DATASHEET DOCUMENT HISTORY 04/24/2001 pgs. 4, 5 and 16 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES 800-345-7015 or 408-727-6116 fax 408-492-8674 for TECH SUPPORT 408 330-1753 e-mail PF Pkg TF Pkg: The SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc. This datasheet has been download from: Datasheets for electronics components.

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DUAL CMOS SyncFIFO

DUAL 256 x 9, DUAL 512 x 9, DUAL 1,024 x 9, DUAL 2,048 x 9, DUAL 4,096 x 9, DUAL 8,192 x 9

IDT72801 IDT72811 IDT72821 IDT72831 IDT72841 IDT72851
.EATURES:
• The IDT72801 is equivalent to two IDT72201 256 x 9 FIFOs
• The IDT72811 is equivalent to two IDT72211 512 x 9 FIFOs
• The IDT72821 is equivalent to two IDT72221 1,024 x 9 FIFOs
• The IDT72831 is equivalent to two IDT72231 2,048 x 9 FIFOs
• The IDT72841 is equivalent to two IDT72241 4,096 x 9 FIFOs
• The IDT72851 is equivalent to two IDT72251 8,192 x 9 FIFOs
• Offers optimal combination of large capacity, high speed,
design flexibility and small footprint
• Ideal for prioritization, bidirectional, and width expansion
applications
• 10 ns read/write cycle time for the IDT72801/72811/72821/72831/
72841 excluding the IDT72851
• 15 ns read/write cycle time for the IDT72851
• Separate control lines and data lines for each FIFO
• Separate Empty, Full, Programmable Almost-Empty and Almost-

Full flags for each FIFO
• Enable puts output data lines in high-impedance state
• Space-saving 64-pin Thin Quad Flat Pack TQFP and Slim Thin

Quad Flatpack STQFP
• Industrial temperature range to +85°C is available

DESCRIPTION:

The IDT72801/72811/72821/72831/72841/72851 are dual synchronous clocked FIFOs. The device is functionally equivalent to two IDT72201/72211/ 72221/72231/72241/72251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins.

Each of the two FIFOs designated FIFO A and FIFO B contained in the

IDT72801/72811/72821/72831/72841/72851 has a 9-bit input data port DA0
- DA8, DB0 - DB8 and a 9-bit output data port QA0 - QA8, QB0 - QB8 . Each
input port is controlled by a free-running clock WCLKA, WCLKB , and two Write Enable pins WENA1, WENA2, WENB1, WENB2 . Data is written into each of
the two arrays on every rising clock edge of the Write Clock WCLKA, WCLKB
when the appropriate write enable pins are asserted.

The output port of each FIFO bank is controlled by its associated clock pin RCLKA, RCLKB and two Read Enable pins RENA1, RENA2, RENB1, RENB2 . The Read Clock can be tied to the Write Clock for single clock operation
or the two clocks can run asynchronous of one another for dual clock operation. An Output Enable pin OEA, OEB is provided on the read port of each FIFO
for three-state output control. Each of the two FIFOs has two fixed flags, Empty EFA, EFB and Full FFA,

FFB . Two programmable flags, Almost-Empty PAEA, PAEB and Almost-Full PAFA, PAFB , are provided for each FIFO bank to improve memory utilization. If not programmed, the programmable flags default to empty+7 for PAEA and PAEB, and full-7 for PAFA and PAFB.

The IDT72801/72811/72821/72831/72841/72851 architecture lends itself
to many flexible configurations such as:
• 2-level priority data buffering
• Bidirectional operation
• Width expansion
• Depth expansion

These FIFOs is fabricated using IDT's high-performance submicron

CMOS technology.
.UNCTIONAL BLOCK DIAGRAM

WCLKA WENA1 WENA2

DA0 - DA8

PAEA

WCLKB

PAFA FFA

WENB1 WENB2

DB0 - DB8

WRITE CONTROL LOGIC

WRITE POINTER

INPUT REGISTER
ORDERING IN.ORMATION

IDT Device Type

X Power

XX Speed

XX Package

Process/ Temperature

Range

BLANK I 1

Commercial 0 C to +70 C Industrial -40 C to +85 C

Thin Quad Flatpack TQFP, PN64-1

Slim Thin Quad Flatpack STQFP, PP64-1

Commercial Only

Clock Cycle Time

Commercial and Industrial tCLK , Speed in

Commercial and Industrial Nanoseconds
72801 72811 72821 72831 72841 72851

Low Power
256 x 9 Dual SyncFIFO 512 x 9 Dual SyncFIFO 1,024 x 9 Dual SyncFIFO 2,048 x 9 Dual SyncFIFO 4,096 x 9 Dual SyncFIFO 8,192 x 9 Dual SyncFIFO

NOTES Industrial temperature range product for 15ns and 25ns speed grade are available as a standard device.
3034 drw 19

DATASHEET DOCUMENT HISTORY
04/24/2001
pgs. 4, 5 and 16

CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES 800-345-7015 or 408-727-6116 fax 408-492-8674
for TECH SUPPORT 408 330-1753
e-mail PF Pkg TF Pkg:

The SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

This datasheet has been download from:

Datasheets for electronics components.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 72841L15PFG Datasheet file may be downloaded here without warranties.

Datasheet ID: 72841L15PFG 637348