IDT723613
Part | Datasheet |
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IDT723613L20PF (pdf) |
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IDT723613L15PF |
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IDT723613L20PFI |
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IDT723613L20PF8 |
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IDT723613L15PF8 |
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IDT723613L20PFI8 |
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IDT723613L20PQF |
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IDT723613L20PQFI |
PDF Datasheet Preview |
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CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 IDT723613 • Free-running CLKA and CLKB may be asynchronous or coincident permits simultaneous reading and writing of data on a single clock edge • 64 x 36 storage capacity FIFO buffering data from Port A to Port B • Mailbox bypass registers in each direction • Dynamic Port B bus sizing of 36 bits long word , 18-bits word , and 9 bits byte • Selection of Big- or Little-Endian format for word and byte bus sizes • Three modes of byte-order swapping on Port B • Programmable Almost-Full and Almost-Empty flags • Microprocessor interface control logic • FF, AF flags synchronized by CLKA • EF, AE flags synchronized by CLKB • Passive parity checking on each Port • Parity Generation can be selected for each Port • Supports clock frequencies up to 67 MHz • Fast access times of 10 ns • Available in 132-pin quad flatpack PQFP or space-saving 120-pin thin quad flatpack TQFP • Industrial temperature range to +85°C is available • Green parts available, see orderng information The IDT723613 is a monolithic, high-speed, low-power, CMOS synchronous clocked FIFO memory which supports clock frequencies up to 67 MHz and has read-access times as fast as 10 ns. The 64 x 36 dual-port SRAM FIFO buffers data from port A to port B. The FIFO has flags to indicate empty and full conditions, and two programmable flags, Almost-Full AF and Almost-Empty AE , to indicate when a selected number of words is stored in memory. FIFO data on port B can be output in 36-bit, 18-bit, and 9-bit formats with a choice of big- or Little-Endian configurations. Three modes of byte-order swapping are possible with any bus-size selection. Communication between each port can bypass the FIFO via two 36-bit mailbox registers. Each mailbox register has FUNCTIONAL BLOCK DIAGRAM Input Register Parity Generation Bus-MatcOhuitnpgutand Byte SRweagipsptinerg Output Register CCLKSAA W/RA ENA MBA Port-A Control Logic RST OEVDEDN/ Device Control Mail 1 Register RAM ARRAY 64 x 36 Parity Gen/Check FF AF FS0 FS1 A0 - A35 Write Pointer Read Pointer Status Flag Logic FIFO Programmable Flag Offset Registers PGA PEFA MBF2 Parity Gen/Check Mail 2 Register IDT and the IDT logo are registered trademarks of Integrated Device Technology Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. MBF1 PEFB 36 64 x 36 B0 - B35 Port-B CPoonrt-rBol CLoongtircol Logic EF AE CLKB CSB W/RB EBNEB SIZ0 SIZ1 SW0 SW1 3145 drw01 ORDERING INFORMATION Device Type Power Speed Package Process/ Temperature Range BLANK Commercial 0°C to +70°C Industrial 40°C to +85°C Green PF PQF Thin Quad Flat Pack TQFP, PN120-1 Plastic Quad Flat Pack PQFP, PQ132-1 15 20 Commercial Only Clock Cycle Time tCLK Com'l & Ind'l Speed in Nanoseconds Low Power 723613 64 x 36 SyncFIFO 3145 drw21 NOTES Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order. Green parts are available. For specific speeds and packages contact your sales office. DATASHEET DOCUMENT HISTORY 03/05/2002 pgs. 1, 6, 8, 9, 24 and 06/14/2005 pgs. 1, 2, 3 and 01/14/2009 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support 408-360-1753 email: |
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