IDT723612L20PFI8

IDT723612L20PFI8 Datasheet

IDT723612

Part	Datasheet
IDT723612L20PFI8	IDT723612L20PFI8 (pdf)

Related Parts	Information
IDT723612L20PQFI	IDT723612L20PQFI
IDT723612L20PFI	IDT723612L20PFI
IDT723612L20PQF	IDT723612L20PQF
IDT723612L20PF8	IDT723612L20PF8
IDT723612L20PF	IDT723612L20PF
IDT723612L15PQF	IDT723612L15PQF
IDT723612L15PF8	IDT723612L15PF8
IDT723612L15PF	IDT723612L15PF
IDT723612L15PQFG	IDT723612L15PQFG

PDF Datasheet Preview
CMOS SyncBiFIFOTM 64 x 36 x 2 IDT723612 • Free-running CLKA and CLKB can be asynchronous or coincident simultaneous reading and writing of data on a single clock edge is permitted • Two independent clocked FIFOs 64 x 36 storage capacity each buffering data in opposite directions • Mailbox bypass Register for each FIFO • Programmable Almost-Full and Almost-Empty Flags • Microprocessor interface control logic • EFA, FFA, AEA, and AFA flags synchronized by CLKA • EFB, FFB, AEB, and AFB flags synchronized by CLKB • Passive parity checking on each port • Parity generation can be selected for each port FUNCTIONAL BLOCK DIAGRAM CLKA CSA W/RA ENA MBA Port-A Control Logic • Supports clock frequencies up to 67 MHz • Fast access times of 10ns • Available in 132-pin plastic quad flat package PQF or space- saving 120-pin thin quad flat package TQFP • Industrial temperature range to +85°C is available • Green parts available, see ordering information The IDT723612 is a monolithic high-speed, low-power CMOS bi-directional clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read access times as fast as 10ns. Two independent 64 x 36 dual-port SRAM FIFOs on board the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags Almost-Full and Mail 1 Register Parity Gen/Check MBF1 PEFB Input Register Parity Generation Output Register RST ODD/ EVEN Device Control FFA AFA FS0 FS1 A0 - A35 EFA AEA RAM ARRAY 64 x 36 Write Read Pointer FIFO1 Status Flag Logic FIFO2 Programmable Flag Offset Register Status Flag Logic Read Write Pointer EFB AEB B0 - B36 FFB AFB Output Register Parity Generation Input Register RAM ARRAY 64 x 36 PEFA MBF2 Parity Gen/Check Mail 2 Register Port-B Control Logic IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. CLKB CSB W/RB ENB MBB 3136 drw01 FEBRUARY 2009 DSC-3136/3 IDT723612 CMOS SYNCBiFIFOTM 64 x 36 x 2 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Almost-Empty to indicate when a selected number of words is stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port and may be ignored if not desired. Parity generation can be selected for data read from each port. Two or more devices can be used in parallel to create wider data paths. This device is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bi-directional interface between microprocessors and/or buses with synchronous control. The Full Flag FFA, FFB and Almost-Full AFA, AFB flag of a FIFO are two-stage synchronized to the port clock that writes data to its array. The Empty Flag EFA, EFB and Almost-Empty AEA, AEB flag of a FIFO are two stage synchronized to the port clock that reads data from its array. The IDT723612 is characterized for operation from 0°C to 70°C. PIN CONFIGURATIONS ORDERING INFORMATION Device Type Power Speed Package Process/ Temperature Range BLANK I 1 Commercial 0°C to +70°C Industrial 40°C to +85°C Green PF PQF Thin Quad Flat Pack TQFP, PN120-1 Plastic Quad Flat Pack PQFP, PQ132-1 Commercial Only Clock Cycle Time tCLK Com'l & Ind'l Speed in Nanoseconds Low Power 723612 64 x 36 x 2 SyncBiFIFO NOTES Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order. Green parts are available. For specific speeds and packages contact your sales office. 3136 drw25 DATASHEET DOCUMENT HISTORY 03/05/2002 pgs. 1, 8, 9 and 06/09/2005 pgs. 1, 2, 3 and 02/13/2009 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, Ca 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for TECH SUPPORT 408-360-1753

PDF Datasheet Preview

CMOS SyncBiFIFOTM 64 x 36 x 2

IDT723612
• Free-running CLKA and CLKB can be asynchronous or coincident simultaneous reading and writing of data on a single clock edge is permitted
• Two independent clocked FIFOs 64 x 36 storage capacity each buffering data in opposite directions
• Mailbox bypass Register for each FIFO
• Programmable Almost-Full and Almost-Empty Flags
• Microprocessor interface control logic
• EFA, FFA, AEA, and AFA flags synchronized by CLKA
• EFB, FFB, AEB, and AFB flags synchronized by CLKB
• Passive parity checking on each port
• Parity generation can be selected for each port

FUNCTIONAL BLOCK DIAGRAM

CLKA CSA

W/RA ENA MBA

Port-A Control Logic
• Supports clock frequencies up to 67 MHz
• Fast access times of 10ns
• Available in 132-pin plastic quad flat package PQF or space-
saving 120-pin thin quad flat package TQFP
• Industrial temperature range to +85°C is available
• Green parts available, see ordering information

The IDT723612 is a monolithic high-speed, low-power CMOS bi-directional clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read access times as fast as 10ns. Two independent 64 x 36 dual-port SRAM FIFOs on board the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags Almost-Full and

Mail 1 Register

Parity Gen/Check

MBF1 PEFB

Input Register Parity Generation Output Register

RST ODD/ EVEN

Device Control

FFA AFA

FS0 FS1 A0 - A35 EFA AEA

RAM ARRAY 64 x 36

Write Read Pointer

FIFO1

Status Flag Logic

FIFO2

Programmable Flag Offset Register

Status Flag Logic

Read Write Pointer

EFB AEB B0 - B36 FFB AFB

Output Register

Parity Generation

Input Register

RAM ARRAY 64 x 36

PEFA MBF2

Parity Gen/Check

Mail 2 Register

Port-B Control Logic

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.

CLKB CSB W/RB ENB MBB
3136 drw01

FEBRUARY 2009

DSC-3136/3

IDT723612 CMOS SYNCBiFIFOTM 64 x 36 x 2

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

Almost-Empty to indicate when a selected number of words is stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port and may be ignored if not desired. Parity generation can be selected for data read from each port. Two or more devices can be used in parallel to create wider data paths. This device is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH
transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bi-directional interface between microprocessors and/or buses with synchronous control.

The Full Flag FFA, FFB and Almost-Full AFA, AFB flag of a FIFO are two-stage synchronized to the port clock that writes data to its array. The Empty Flag EFA, EFB and Almost-Empty AEA, AEB flag of a FIFO are two stage synchronized to the port clock that reads data from its array.

The IDT723612 is characterized for operation from 0°C to 70°C.

PIN CONFIGURATIONS
ORDERING INFORMATION

Device Type Power

Speed Package

Process/ Temperature

Range

BLANK I 1

Commercial 0°C to +70°C Industrial 40°C to +85°C

Green

PF PQF

Thin Quad Flat Pack TQFP, PN120-1 Plastic Quad Flat Pack PQFP, PQ132-1

Commercial Only Clock Cycle Time tCLK

Com'l & Ind'l

Speed in Nanoseconds

Low Power
723612 64 x 36 x 2 SyncBiFIFO

NOTES Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order. Green parts are available. For specific speeds and packages contact your sales office.
3136 drw25

DATASHEET DOCUMENT HISTORY
03/05/2002
pgs. 1, 8, 9 and
06/09/2005
pgs. 1, 2, 3 and
02/13/2009

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, Ca 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775
for TECH SUPPORT 408-360-1753

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT723612L20PFI8 Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT723612L20PFI8 637345