IDT723611L15PF

IDT723611L15PF Datasheet

IDT723611

Part	Datasheet
IDT723611L15PF	IDT723611L15PF (pdf)

Related Parts	Information
IDT723611L20PQF	IDT723611L20PQF
IDT723611L15PF8	IDT723611L15PF8
IDT723611L20PF	IDT723611L20PF
IDT723611L20PFI8	IDT723611L20PFI8
IDT723611L15PQF	IDT723611L15PQF
IDT723611L20PQFI	IDT723611L20PQFI
IDT723611L20PFI	IDT723611L20PFI
IDT723611L20PF8	IDT723611L20PF8

PDF Datasheet Preview
CMOS SyncFIFOTM 64 x 36 IDT723611 FEATURES: • Free-running CLKA and CLKB may be asynchronous or coincident permits simultaneous reading and writing of data on a single clock edge • 64 x 36 storage capacity • Synchronous data buffering from Port A to Port B • Mailbox bypass register in each direction • Programmable Almost-Full AF and Almost-Empty AE flags • Microprocessor Interface Control Logic • Full Flag FF and Almost-Full AF flags synchronized by CLKA • Empty Flag EF and Almost-Empty AE flags synchronized by CLKB • Passive parity checking on each Port • Parity Generation can be selected for each Port • Supports clock frequencies up to 67MHz • Fast access times of 10ns • Available in 132-pin Plastic Quad Flatpack PQF or space-saving 120-pin Thin Quad Flatpack PF • Industrial temperature range to +85°C is available • Green parts available, see ordering information DESCRIPTION: The IDT723611 is a monolithic, high-speed, low-power, CMOS Synchronous clocked FIFO memory which supports clock frequencies up to 67MHz and has read access times as fast as 10ns. The 64 x 36 dual-port FIFO buffers data from Port A to Port B. The FIFO has flags to indicate empty and full conditions, and two programmable flags, Almost-Full AF and Almost-Empty AE , to indicate when a selected number of words is stored in memory. Communication between each port can take place through two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port and may be ignored if not desired. Parity generation can be selected for data read from each port. Two or more devices may be used in parallel to create wider data paths. The IDT723611 is a synchronous clocked FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. FUNCTIONAL BLOCK DIAGRAM Input Register Parity Generation Output Register CLKA CSA W/RA ENA MBA Port-A Control Logic RST ODD/ EVEN Reset Logic A0 - A35 FF AF FS0 FS1 FIFO Mail 1 Register RAM ARRAY 64 x 36 Write Read Pointer Status Flag Logic Programmable Flag Offset Registers Parity Gen/Check MBF1 PEFB PGB B0 - B35 EF AE PEFA MBF2 Parity Gen/Check Mail 2 Register IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBIFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. Port-B Control Logic CLKB CSB W/RB ENB MBB 3024 drw 01 FEBRUARY 2009 DSC-3024/3 IDT723611 CMOS SyncFIFOTM 64 x 36 DESCRIPTION CONTINUED The Full Flag FF and Almost-Full AF flag of the FIFO are two-stage synchronized to the port clock that writes data into its array CLKA . The Empty COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Flag EF and Almost-Empty AE flag of the FIFO are two-stage synchronized to the port clock that reads data from its array. The IDT723611 is characterized for operation from 0°C to 70°C. 64 x 36 ORDERING INFORMATION Device Type Power Speed Package Process/ Temperature Range BLANK Commercial 0°C to +70°C Industrial 40°C to +85°C Green PF PQF 15 20 Thin Quad Flat Pack TQFP, PN120-1 Plastic Quad Flat Pack PQFP, PQ132-1 Commercial Only Clock Cycle Time tCLK Com'l & Ind'l Speed in Nanoseconds Low Power 723611 64 x 36 Synchronous FIFO NOTES Industrial temperature range product for 20ns speed grade is avaiable as a standard device. All other speed grades are available by special order. Green parts are available. For specific speeds and packages contact your sales office. 3024 drw 19 DATASHEET DOCUMENT HISTORY 03/05/2002 pgs. 1, 6, 8, 9 and 06/01/2005 pgs. 1,2,3 and 02/13/2009 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, Ca 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for TECH SUPPORT 408-360-1753

PDF Datasheet Preview

CMOS SyncFIFOTM 64 x 36

IDT723611

FEATURES:
• Free-running CLKA and CLKB may be asynchronous or coincident permits simultaneous reading and writing of data on a single clock edge
• 64 x 36 storage capacity
• Synchronous data buffering from Port A to Port B
• Mailbox bypass register in each direction
• Programmable Almost-Full AF and Almost-Empty AE flags
• Microprocessor Interface Control Logic
• Full Flag FF and Almost-Full AF flags synchronized by CLKA
• Empty Flag EF and Almost-Empty AE flags synchronized by

CLKB
• Passive parity checking on each Port
• Parity Generation can be selected for each Port
• Supports clock frequencies up to 67MHz
• Fast access times of 10ns
• Available in 132-pin Plastic Quad Flatpack PQF or space-saving
120-pin Thin Quad Flatpack PF
• Industrial temperature range to +85°C is available
• Green parts available, see ordering information

DESCRIPTION:

The IDT723611 is a monolithic, high-speed, low-power, CMOS Synchronous clocked FIFO memory which supports clock frequencies up to 67MHz and has read access times as fast as 10ns. The 64 x 36 dual-port FIFO buffers data from Port A to Port B. The FIFO has flags to indicate empty and full conditions, and two programmable flags, Almost-Full AF and Almost-Empty AE , to indicate when a selected number of words is stored in memory. Communication between each port can take place through two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port and may be ignored if not desired. Parity generation can be selected for data read from each port. Two or more devices may be used in parallel to create wider data paths.

The IDT723611 is a synchronous clocked FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.

FUNCTIONAL BLOCK DIAGRAM

Input Register Parity Generation Output Register

CLKA CSA

W/RA ENA MBA

Port-A Control Logic

RST ODD/ EVEN

Reset Logic

A0 - A35

FF AF

FS0 FS1

FIFO

Mail 1 Register

RAM ARRAY 64 x 36

Write Read Pointer

Status Flag Logic

Programmable Flag Offset Registers

Parity Gen/Check

MBF1 PEFB PGB

B0 - B35 EF AE

PEFA MBF2

Parity Gen/Check

Mail 2 Register

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBIFIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.

Port-B Control Logic

CLKB CSB W/RB ENB MBB
3024 drw 01

FEBRUARY 2009

DSC-3024/3

IDT723611 CMOS SyncFIFOTM 64 x 36

DESCRIPTION CONTINUED

The Full Flag FF and Almost-Full AF flag of the FIFO are two-stage synchronized to the port clock that writes data into its array CLKA . The Empty

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

Flag EF and Almost-Empty AE flag of the FIFO are two-stage synchronized to the port clock that reads data from its array.

The IDT723611 is characterized for operation from 0°C to 70°C.
64 x 36
ORDERING INFORMATION

Device Type Power Speed Package

Process/ Temperature

Range

BLANK Commercial 0°C to +70°C

Industrial 40°C to +85°C

Green

PF PQF
15 20

Thin Quad Flat Pack TQFP, PN120-1 Plastic Quad Flat Pack PQFP, PQ132-1

Commercial Only Clock Cycle Time tCLK

Com'l & Ind'l

Speed in Nanoseconds

Low Power
723611 64 x 36 Synchronous FIFO

NOTES Industrial temperature range product for 20ns speed grade is avaiable as a standard device. All other speed grades are available by special order. Green parts are available. For specific speeds and packages contact your sales office.
3024 drw 19

DATASHEET DOCUMENT HISTORY
03/05/2002
pgs. 1, 6, 8, 9 and
06/01/2005
pgs. 1,2,3 and
02/13/2009

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, Ca 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775
for TECH SUPPORT 408-360-1753

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT723611L15PF Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT723611L15PF 637344