72221L25JG

72221L25JG Datasheet

IDT72421, IDT72201 IDT72211, IDT72221 IDT72231, IDT72241

Part	Datasheet
72221L25JG	72221L25JG (pdf)

PDF Datasheet Preview
CMOS SyncFIFO 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 IDT72421, IDT72201 IDT72211, IDT72221 IDT72231, IDT72241 IDT72251 FEATURES: • 64 x 9-bit organization IDT72421 • 256 x 9-bit organization IDT72201 • 512 x 9-bit organization IDT72211 • 1,024 x 9-bit organization IDT72221 • 2,048 x 9-bit organization IDT72231 • 4,096 x 9-bit organization IDT72241 • 8,192 x 9-bit organization IDT72251 • 10 ns read/write cycle time • Read and Write Clocks can be independent • Dual-Ported zero fall-through time architecture • Empty and Full Flags signal FIFO status • Programmable Almost-Empty and Almost-Full flags can be set to any depth • Programmable Almost-Empty and Almost-Full flags default to Empty+7, and Full-7, respectively • Output enable puts output data bus in high-impedance state • Advanced submicron CMOS technology • Available in the 32-pin plastic leaded chip carrier PLCC and 32-pin Thin Quad Flat Pack TQFP • For through-hole product please see the IDT72420/72200/72210/ 72220/72230/72240 data sheet • Industrial temperature range to +85°C is available DESCRIPTION: The SyncFIFO are very high-speed, low-power First-In, First-Out FIFO memories with clocked read and write controls. These devices have a 64, 256, 512, 1,024, 2,048, 4,096, and 8,192 x 9-bit memory array, respectively. These FIFOs are applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. These FIFOs have 9-bit input and output ports. The input port is controlled by a free-running clock WCLK , and two write enable pins WEN1, WEN2 . Data is written into the Synchronous FIFO on every rising clock edge when the write enable pins are asserted. The output port is controlled by another clock pin RCLK and two read enable pins REN1, REN2 . The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. An output enable pin OE is provided on the read port for three-state control of the output. The Synchronous FIFOs have two fixed flags, Empty EF and Full FF . Two programmable flags, Almost-Empty PAE and Almost-Full PAF , are provided for improved system control. The programmable flags default to Empty+7 and Full-7 for PAE and PAF, respectively. The programmable flag offset loading is controlled by a simple state machine and is initiated by asserting the load pin LD . These FIFOs are fabricated using IDT’s high-speed submicron CMOS technology. FUNCTIONAL BLOCK DIAGRAM WCLK D0 - D8 WEN1 WEN2 INPUT REGISTER OFFSET REGISTER WRITE CONTROL LOGIC WRITE POINTER RAM ARRAY 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 FLAG LOGIC READ POINTER READ CONTROL LOGIC RESET LOGIC RS OUTPUT REGISTER OE Q0 - Q8 RCLK REN1 REN2 2655 drw01 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. SEPTEMBER 2002 DSC-2655/2 CMOS SyncFIFO 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 PIN CONFIGURATION ORDERING INFORMATION Device Type Power Speed Package X Process/ Temperature Range BLANK Commercial 0°C to +70°C Industrial -40° to +85°C Plastic Leaded Chip Carrier PLCC, J32-1 Thin Quad Flat Pack TQFP, PR32-1 10 15 25 Commercial Only Commercial & Industrial Commercial & Industrial Clock Cycle Time tCLK Speed in Nanoseconds Low Power 72421 72201 72211 72221 72231 72241 72251 64 x 9 SyncFIFO 256 x 9 SyncFIFO 512 x 9 SyncFIFO 1,024 x 9 SyncFIFO 2,048 x 9 SyncFIFO 4,096 x 9 SyncFIFO 8,192 x 9 SyncFIFO NOTES Industrial temperature range product for the 15ns and 25ns speed grades are available as standard product. 2655 drw18 DATASHEET DOCUMENT HISTORY 10/03/2000 05/01/2001 pgs. 2, 3, 4 and pgs. 1, 2, 3, 4 and CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES 800-345-7015 or 408-727-6116 fax 408-492-8674 for Tech Support 408-330-1753

PDF Datasheet Preview

CMOS SyncFIFO 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

IDT72421, IDT72201 IDT72211, IDT72221 IDT72231, IDT72241

IDT72251

FEATURES:
• 64 x 9-bit organization IDT72421
• 256 x 9-bit organization IDT72201
• 512 x 9-bit organization IDT72211
• 1,024 x 9-bit organization IDT72221
• 2,048 x 9-bit organization IDT72231
• 4,096 x 9-bit organization IDT72241
• 8,192 x 9-bit organization IDT72251
• 10 ns read/write cycle time
• Read and Write Clocks can be independent
• Dual-Ported zero fall-through time architecture
• Empty and Full Flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags can be set
to any depth
• Programmable Almost-Empty and Almost-Full flags default to

Empty+7, and Full-7, respectively
• Output enable puts output data bus in high-impedance state
• Advanced submicron CMOS technology
• Available in the 32-pin plastic leaded chip carrier PLCC and
32-pin Thin Quad Flat Pack TQFP
• For through-hole product please see the IDT72420/72200/72210/
72220/72230/72240 data sheet
• Industrial temperature range to +85°C is available

DESCRIPTION:

The SyncFIFO are very high-speed, low-power First-In, First-Out FIFO memories with clocked read and write controls. These devices have a 64, 256, 512, 1,024, 2,048, 4,096, and 8,192 x 9-bit memory array, respectively. These FIFOs are applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication.

These FIFOs have 9-bit input and output ports. The input port is controlled by a free-running clock WCLK , and two write enable pins WEN1, WEN2 . Data is written into the Synchronous FIFO on every rising clock edge when the write enable pins are asserted. The output port is controlled by another clock pin RCLK and two read enable pins REN1, REN2 . The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. An output enable pin OE is provided on the read port for three-state control of the output.

The Synchronous FIFOs have two fixed flags, Empty EF and Full FF . Two programmable flags, Almost-Empty PAE and Almost-Full PAF , are provided for improved system control. The programmable flags default to Empty+7 and Full-7 for PAE and PAF, respectively. The programmable flag offset loading is controlled by a simple state machine and is initiated by asserting the load pin LD .

These FIFOs are fabricated using IDT’s high-speed submicron CMOS technology.

FUNCTIONAL BLOCK DIAGRAM

WCLK

D0 - D8

WEN1

WEN2

INPUT REGISTER

OFFSET REGISTER

WRITE CONTROL LOGIC

WRITE POINTER

RAM ARRAY 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9,
8,192 x 9

FLAG

LOGIC

READ POINTER

READ CONTROL LOGIC

RESET LOGIC RS

OUTPUT REGISTER OE

Q0 - Q8

RCLK REN1 REN2
2655 drw01

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.

SEPTEMBER 2002

DSC-2655/2

CMOS SyncFIFO 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

PIN CONFIGURATION
ORDERING INFORMATION

Device Type Power Speed Package

X Process/ Temperature Range

BLANK Commercial 0°C to +70°C

Industrial -40° to +85°C

Plastic Leaded Chip Carrier PLCC, J32-1

Thin Quad Flat Pack TQFP, PR32-1
10 15 25

Commercial Only Commercial & Industrial Commercial & Industrial

Clock Cycle Time tCLK Speed in Nanoseconds

Low Power
72421 72201 72211 72221 72231 72241 72251
64 x 9 SyncFIFO 256 x 9 SyncFIFO 512 x 9 SyncFIFO 1,024 x 9 SyncFIFO 2,048 x 9 SyncFIFO 4,096 x 9 SyncFIFO 8,192 x 9 SyncFIFO

NOTES Industrial temperature range product for the 15ns and 25ns speed grades are available as standard product.
2655 drw18

DATASHEET DOCUMENT HISTORY
10/03/2000 05/01/2001
pgs. 2, 3, 4 and pgs. 1, 2, 3, 4 and

CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES 800-345-7015 or 408-727-6116 fax 408-492-8674
for Tech Support 408-330-1753

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 72221L25JG Datasheet file may be downloaded here without warranties.

Datasheet ID: 72221L25JG 637343