IDT71V3579YS85PF

IDT71V3579YS85PF Datasheet

IDT71V3577YS IDT71V3579YS IDT71V3577YSA IDT71V3579YSA

Part	Datasheet
IDT71V3579YS85PF	IDT71V3579YS85PF (pdf)

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IDT71V3577YS75PF8	IDT71V3577YS75PF8
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IDT71V3579S65PF	IDT71V3579S65PF
IDT71V3577YS85PFI8	IDT71V3577YS85PFI8
IDT71V3577YS85PFI	IDT71V3577YS85PFI
IDT71V3577YS85PF8	IDT71V3577YS85PF8
IDT71V3577YS85PF	IDT71V3577YS85PF
IDT71V3577YS80PFI8	IDT71V3577YS80PFI8
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IDT71V3577YS80PF8	IDT71V3577YS80PF8
IDT71V3577YS75PFG	IDT71V3577YS75PFG
IDT71V3579YS85PF8	IDT71V3579YS85PF8
IDT71V3577YS75PF	IDT71V3577YS75PF
IDT71V3577YS65PFG	IDT71V3577YS65PFG
IDT71V3579YS65PFG	IDT71V3579YS65PFG
IDT71V3577YS80PF	IDT71V3577YS80PF
71V3577YS85PFG	71V3577YS85PFG

PDF Datasheet Preview
128K X 36, 256K X 18 3.3V Synchronous SRAMs 3.3V I/O, Flow-Through Outputs Burst Counter, Single Cycle Deselect IDT71V3577YS IDT71V3579YS IDT71V3577YSA IDT71V3579YSA 128K x 36, 256K x 18 memory configurations Supports fast access times: Commercial: 6.5ns up to 133MHz clock frequency 7.5ns up to 117MHz clock frequency Commercial and Industrial: 8.0ns up to 100MHz clock frequency 8.5ns up to 87MHz clock frequency LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control GW , byte write enable BWE , and byte writes BWx 3.3V core power supply Power down controlled by ZZ input 3.3V I/O Optional - Boundary Scan JTAG Interface IEEE compliant Packaged in a JEDEC Standard 100-pin plastic thin quad flatpack TQFP , 119 ball grid array BGA and 165 fine pitch ball grid array The IDT71V3577/79 are high-speed SRAMs organized as 128K x 36/256K x The IDT71V3577/79 SRAMs contain write, data, address and control registers. There are no registers in the data output path flow-through architecture . Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the IDT71V3577/79 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will flow-through from the array after a clock-to-data access time delay from the rising clock edge of the same cycle. If burst mode operation is selected ADV=LOW , the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The order of these three addresses are defined by the internal burst counter and the LBO input pin. The IDT71V3577/79 SRAMs utilize IDT’s latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack TQFP as well as a 119 ball grid array BGA and a 165 fine pitch ball grid array fBGA . Pin Description Summary A0-A17 Address Inputs Input Synchronous Chip Enable Input Synchronous CS0, CS1 Chip Selects Input Synchronous Output Enable Input Asynchronous Global Write Enable Input Synchronous Byte Write Enable Input Synchronous BW1, BW2, BW3, BW4 1 Individual Byte Write Selects Input Synchronous Ordering Information IDT XXX Device Type Power Speed Package Process/ Temperature Range Blank I Commercial 0°C to +70°C Industrial -40°C to +85°C PF** BG BQ 65* 75* 80 85 Restricted hazardous substance device 100-pin Plastic Thin Quad Flatpack TQFP 119 Ball Grid Array BGA 165 Fine Pitch Ball Grid Array fBGA Access Time in Tenths of Nanoseconds Standard Power Standard Power with JTAG Interface Y Generation die step 71V3577 128K x 36 Flow-Through Burst Synchronous SRAM with 3.3V 71V3579 I/O 256K x 18 Flow-Through Burst Synchronous SRAM with 3.3V 6450 drw 12 Commercial temperature range only. * JTAG SA version is not available with 100 pin TQFP package Package Information 100-Pin Thin Quad Plastic Flatpack TQFP 119 Ball Grid Array BGA 165 Fine Pitch Ball Grid Array fBGA Information available on the IDT website IDT71V3577YS_79YS, IDT71V3577YSA_79YSA, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges Datasheet Document History 01/30/04 04/17/06 Page p. 21 Description Released Y generation die step datasheet Added green Restricted hazardous substance device to the datasheet. CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 The IDT logo is a registered trademark of Integrated Device Technology, Inc. for Tech Support 408-284-4532

PDF Datasheet Preview

128K X 36, 256K X 18 3.3V Synchronous SRAMs 3.3V I/O, Flow-Through Outputs Burst Counter, Single Cycle Deselect

IDT71V3577YS IDT71V3579YS IDT71V3577YSA IDT71V3579YSA
128K x 36, 256K x 18 memory configurations Supports fast access times:

Commercial:
6.5ns up to 133MHz clock frequency
7.5ns up to 117MHz clock frequency

Commercial and Industrial:
8.0ns up to 100MHz clock frequency
8.5ns up to 87MHz clock frequency LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control GW , byte write
enable BWE , and byte writes BWx 3.3V core power supply Power down controlled by ZZ input 3.3V I/O Optional - Boundary Scan JTAG Interface IEEE
compliant Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack TQFP , 119 ball grid array BGA and 165 fine pitch ball
grid array

The IDT71V3577/79 are high-speed SRAMs organized as 128K x 36/256K x The IDT71V3577/79 SRAMs contain write, data, address and control registers. There are no registers in the data output path flow-through architecture . Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle.

The burst mode feature offers the highest level of performance to the system designer, as the IDT71V3577/79 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will flow-through from the array after a clock-to-data access time delay from the rising clock edge of the same cycle. If burst mode operation is selected ADV=LOW , the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The order of these three addresses are defined by the internal burst counter and the LBO input pin.

The IDT71V3577/79 SRAMs utilize IDT’s latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack TQFP as well as a 119 ball grid array BGA and a 165 fine pitch ball grid array fBGA .

Pin Description Summary

A0-A17

Address Inputs

Input

Synchronous

Chip Enable

Input

Synchronous

CS0, CS1

Chip Selects

Input

Synchronous

Output Enable

Input

Asynchronous

Global Write Enable

Input

Synchronous

Byte Write Enable

Input

Synchronous

BW1, BW2, BW3, BW4 1

Individual Byte Write Selects

Input

Synchronous
Ordering Information

IDT XXX

Device Type

Power Speed Package

Process/ Temperature

Range

Blank I

Commercial 0°C to +70°C Industrial -40°C to +85°C

PF** BG BQ
65* 75* 80 85

Restricted hazardous substance device
100-pin Plastic Thin Quad Flatpack TQFP 119 Ball Grid Array BGA 165 Fine Pitch Ball Grid Array fBGA

Access Time in Tenths of Nanoseconds

Standard Power Standard Power with JTAG Interface

Y Generation die step
71V3577 128K x 36 Flow-Through Burst Synchronous SRAM with 3.3V
71V3579 I/O
256K x 18 Flow-Through Burst Synchronous SRAM with 3.3V
6450 drw 12
*Commercial temperature range only.
** JTAG SA version is not available with 100 pin TQFP package

Package Information
100-Pin Thin Quad Plastic Flatpack TQFP 119 Ball Grid Array BGA 165 Fine Pitch Ball Grid Array fBGA Information available on the IDT website

IDT71V3577YS_79YS, IDT71V3577YSA_79YSA, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Datasheet Document History
01/30/04
04/17/06

Page p. 21

Description Released Y generation die step datasheet Added green Restricted hazardous substance device to the datasheet.

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775

The IDT logo is a registered trademark of Integrated Device Technology, Inc.
for Tech Support 408-284-4532

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT71V3579YS85PF Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT71V3579YS85PF 637337