IDT71V3578S150PFI8

IDT71V3578S150PFI8 Datasheet

IDT71V3576YS IDT71V3578YS IDT71V3576YSA IDT71V3578YSA

Part	Datasheet
IDT71V3578S150PFI8	IDT71V3578S150PFI8 (pdf)

Related Parts	Information
IDT71V3578YS133PF8	IDT71V3578YS133PF8
IDT71V3578S133PF	IDT71V3578S133PF
IDT71V3578YS133PFI	IDT71V3578YS133PFI
IDT71V3578YS133PF	IDT71V3578YS133PF
IDT71V3578S150PFI	IDT71V3578S150PFI
IDT71V3578S150PF8	IDT71V3578S150PF8
IDT71V3578S150PF	IDT71V3578S150PF
IDT71V3578S133PFI8	IDT71V3578S133PFI8
IDT71V3578S133PFI	IDT71V3578S133PFI
IDT71V3578S133PF8	IDT71V3578S133PF8
IDT71V3578YS133PFI8	IDT71V3578YS133PFI8

PDF Datasheet Preview
128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect IDT71V3576YS IDT71V3578YS IDT71V3576YSA IDT71V3578YSA 128K x 36, 256K x 18 memory configurations Supports high system speed: Commercial and Industrial: 150MHz 3.8ns clock access time 133MHz 4.2ns clock access time LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control GW , byte write enable BWE , and byte writes BWx 3.3V core power supply Power down controlled by ZZ input 3.3V I/O Optional - Boundary Scan JTAG Interface IEEE compliant Packaged in a JEDEC Standard 100-pin plastic thin quad flatpack TQFP , 119 ball grid array BGA and 165 fine pitch ball grid array fBGA The IDT71V3576/78 are high-speed SRAMs organized as 128K x 36/256K x The IDT71V3576/78 SRAMs contain write, data, address and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the IDT71V3576/78 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will be pipelined for one cycle before it is available on the next rising clock edge. If burst mode operation is selected ADV=LOW , the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The order of these three addresses are defined by the internal burst counter and the LBO input pin. The IDT71V3576/78 SRAMs utilize IDT’s latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack TQFP as well as a 119 ball grid array BGA and a 165 fine pitch ball grid array fBGA . Pin Description Summary A0-A17 Address Inputs Input Synchronous Chip Enable Input Synchronous CS0, CS1 Chip Selects Input Synchronous Output Enable Input Asynchronous Global Write Enable Input Synchronous Byte Write Enable Input Synchronous BW1, BW2, BW3, BW4 1 Individual Byte Write Selects Input Synchronous Clock Input Burst Address Advance Ordering Information IDT XXX X Device Type Power Speed Package Process/ Temperature Range Blank I Commercial 0°C to +70°C Industrial -40°C to +85°C 100-pin Plastic Thin Quad Flatpack TQFP 119 Ball Grid Array BGA 165 Fine Pitch Ball Grid Array fBGA 150 133 Frequency in Megahertz Standard Power Standard Power with JTAG Interface 71V3576 71V3578 Y generation die step 128K x 36 Pipelined Burst Synchronous SRAM with 3.3V I/O 256K x 18 Pipelined Burst Synchronous SRAM with 3.3V I/O 6446 drw 13 * Note JTAG SA version is not available with 100-pin TQFP package. Package Information 100-Pin Thin Quad Plastic Flatpack TQFP 119 Ball Grid Array BGA 165 Fine Pitch Ball Grid Array fBGA Information available on the IDT website IDT71V3576Y 128K x 36 , IDT71V3578Y 256K x 18 , 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges Datasheet Document History 11/30/03 05/21/04 p.4 Released Y generation die step datasheet Updated Absolute Maximum Ratings table on Commercial rating from -0 to +70 to 0 to CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 The IDT logo is a registered trademark of Integrated Device Technology, Inc. for Tech Support 800-345-7015

PDF Datasheet Preview

128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect

IDT71V3576YS IDT71V3578YS IDT71V3576YSA IDT71V3578YSA
128K x 36, 256K x 18 memory configurations Supports high system speed:

Commercial and Industrial:
150MHz 3.8ns clock access time
133MHz 4.2ns clock access time LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control GW , byte write
enable BWE , and byte writes BWx 3.3V core power supply Power down controlled by ZZ input 3.3V I/O Optional - Boundary Scan JTAG Interface IEEE
compliant Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack TQFP , 119 ball grid array BGA and 165 fine pitch ball
grid array fBGA

The IDT71V3576/78 are high-speed SRAMs organized as 128K x 36/256K x The IDT71V3576/78 SRAMs contain write, data, address and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle.

The burst mode feature offers the highest level of performance to the system designer, as the IDT71V3576/78 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will be pipelined for one cycle before it is available on the next rising clock edge. If burst mode operation is selected ADV=LOW , the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The order of these three addresses are defined by the internal burst counter and the LBO input pin.

The IDT71V3576/78 SRAMs utilize IDT’s latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack TQFP as well as a 119 ball grid array BGA and a 165 fine pitch ball grid array fBGA .

Pin Description Summary

A0-A17

Address Inputs

Input

Synchronous

Chip Enable

Input

Synchronous

CS0, CS1

Chip Selects

Input

Synchronous

Output Enable

Input

Asynchronous

Global Write Enable

Input

Synchronous

Byte Write Enable

Input

Synchronous

BW1, BW2, BW3, BW4 1

Individual Byte Write Selects

Input

Synchronous

Clock

Input

Burst Address Advance
Ordering Information

IDT XXX X

Device Type

Power

Speed

Package Process/ Temperature Range

Blank I

Commercial 0°C to +70°C Industrial -40°C to +85°C
100-pin Plastic Thin Quad Flatpack TQFP
119 Ball Grid Array BGA
165 Fine Pitch Ball Grid Array fBGA
150 133

Frequency in Megahertz

Standard Power

Standard Power with JTAG Interface
71V3576 71V3578

Y generation die step
128K x 36 Pipelined Burst Synchronous SRAM with 3.3V I/O 256K x 18 Pipelined Burst Synchronous SRAM with 3.3V I/O
6446 drw 13
* Note JTAG SA version is not available with 100-pin TQFP package.

Package Information
100-Pin Thin Quad Plastic Flatpack TQFP 119 Ball Grid Array BGA 165 Fine Pitch Ball Grid Array fBGA Information available on the IDT website

IDT71V3576Y 128K x 36 , IDT71V3578Y 256K x 18 , 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Datasheet Document History
11/30/03 05/21/04 p.4

Released Y generation die step datasheet Updated Absolute Maximum Ratings table on Commercial rating from -0 to +70 to 0 to

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775

The IDT logo is a registered trademark of Integrated Device Technology, Inc.
for Tech Support 800-345-7015

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT71V3578S150PFI8 Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT71V3578S150PFI8 637335