IDT71V2559S85BG8

IDT71V2559S85BG8 Datasheet

IDT71V2557 IDT71V2559

Part	Datasheet
IDT71V2559S85BG8	IDT71V2559S85BG8 (pdf)

Related Parts	Information
IDT71V2559S75PFG8	IDT71V2559S75PFG8
IDT71V2559S75PFG	IDT71V2559S75PFG
IDT71V2559S85PFG8	IDT71V2559S85PFG8
IDT71V2559S85PFG	IDT71V2559S85PFG
IDT71V2559S80PFG8	IDT71V2559S80PFG8
IDT71V2559S80PFG	IDT71V2559S80PFG
IDT71V2559S80BG8	IDT71V2559S80BG8
IDT71V2559S75BG	IDT71V2559S75BG
IDT71V2559S75BG8	IDT71V2559S75BG8
IDT71V2559S75PF	IDT71V2559S75PF
IDT71V2559S80BG	IDT71V2559S80BG
IDT71V2559S80PF	IDT71V2559S80PF
IDT71V2559S80PF8	IDT71V2559S80PF8
IDT71V2559S85BG	IDT71V2559S85BG
IDT71V2559S85PF	IDT71V2559S85PF
IDT71V2559S85PF8	IDT71V2559S85PF8
IDT71V2559S75PF8	IDT71V2559S75PF8

PDF Datasheet Preview
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter, Flow-Through Outputs IDT71V2557 IDT71V2559 x 128K x 36, 256K x 18 memory configurations x Supports high performance system speed - 100 MHz ns Clock-to-Data Access x ZBTTM Feature - No dead cycles between write and read cycles x Internally synchronized output buffer enable eliminates the need to control OE x Single R/W READ/WRITE control pin x 4-word burst capability Interleaved or linear x Individual byte write BW1 - BW4 control May tie active x Three chip enables for simple depth expansion x 3.3V power supply ±5% x 2.5V ±5% I/O Supply VDDQ x Packaged in a JEDEC Standard 100-pin plastic thin quad flatpack TQFP , 119 ball grid array BGA and 165 fine pitch ball grid array fBGA The IDT71V2557/59 are 3.3V high-speed 4,718,592-bit Megabit synchronous SRAMs organized as 128K x 36 / 256K x They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or Zero Bus Turnaround. Address and control signals are applied to the SRAM during one clock cycle, and on the next clock cycle the associated data cycle occurs, be it read or write. The IDT71V2557/59 contain address, data-in and control signal registers. The outputs are flow-through no output data register . Output enable is the only asynchronous signal and can be used to disable the outputs at any given time. A Clock Enable CEN pin allows operation of the IDT71V2557/59 to be suspended as long as necessary. All synchronous inputs are ignored when CEN is high and the internal device registers will hold their previous values. There are three chip enable pins CE1, CE2, CE2 that allow the user to deselect the device when desired. If any one of these three is not asserted when ADV/LD is low, no new memory operation can be initiated. However, any pending data transfers reads or writes will be completed. The data bus will tri-state one cycle after the chip is deselected or a write is initiated. The IDT71V2557/59 have an on-chip burst counter. In the burst mode, the IDT71V2557/59 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address ADV/LD = LOW or increment the internal burst counter ADV/LD = HIGH . The IDT71V2557/59 SRAMs utilize IDT's latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack TQFP as well as a 119 ball grid array BGA and a 165 fine pitch ball grid array fBGA . Pin Description Summary A0-A17 Address Inputs CE1, CE2, CE2 Chip Enables Output Enable Read/Write Signal Clock Enable Input Synchronous Input Synchronous Input Asynchronous Input Ordering Information IDT XXXX Device Type Power Speed Package Process/ Temperature Range Blank Commercial 0°C to +70°C Industrial -40°C to +85°C PF 100-pin Plastic Thin Quad Flatpack TQFP BG 119 Ball Grid Array BGA BQ 165 Fine Pitch Ball Grid Array fBGA Access time tCD in tenths of nanoseconds IDT71V2557 128Kx36 Flow-Through ZBT SRAM with 2.5V I/O IDT71V2559 256Kx18 Flow-Through ZBT SRAM with 2.5V I/O * Commercial temperature range only. 4878 drw 12 IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges Datasheet Document History 6/30/99 8/23/99 12/31/99 05/02/00 05/26/00 07/26/00 10/25/00 Pg. 5, 6 Pg. 7 Pg. 15 Pg. 21 Pg. 23 Pg. 5, 14, 15, 22 Pg. 5,6 Pg. 5,6,7 Pg. 6 Pg. 21 Pg. 23 Pg. 5-7 Pg. 8 Pg. 23 Pg. 8 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES 800-345-7015 or 408-727-6116 fax 408-492-8674 The IDT logo is a registered trademark of Integrated Device Technology, Inc. for Tech Support 800-544-7726, x4033

PDF Datasheet Preview

128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter, Flow-Through Outputs

IDT71V2557 IDT71V2559
x 128K x 36, 256K x 18 memory configurations x Supports high performance system speed - 100 MHz
ns Clock-to-Data Access x ZBTTM Feature - No dead cycles between write and read
cycles x Internally synchronized output buffer enable eliminates the
need to control OE x Single R/W READ/WRITE control pin x 4-word burst capability Interleaved or linear x Individual byte write BW1 - BW4 control May tie active x Three chip enables for simple depth expansion x 3.3V power supply ±5% x 2.5V ±5% I/O Supply VDDQ x Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack TQFP , 119 ball grid array BGA and 165 fine pitch ball grid array fBGA

The IDT71V2557/59 are 3.3V high-speed 4,718,592-bit Megabit synchronous SRAMs organized as 128K x 36 / 256K x They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or Zero Bus Turnaround.

Address and control signals are applied to the SRAM during one clock cycle, and on the next clock cycle the associated data cycle occurs, be it read or write.

The IDT71V2557/59 contain address, data-in and control signal
registers. The outputs are flow-through no output data register . Output
enable is the only asynchronous signal and can be used to disable the
outputs at any given time. A Clock Enable CEN pin allows operation of the IDT71V2557/59
to be suspended as long as necessary. All synchronous inputs are ignored when CEN is high and the internal device registers will hold
their previous values. There are three chip enable pins CE1, CE2, CE2 that allow the
user to deselect the device when desired. If any one of these three is not asserted when ADV/LD is low, no new memory operation can be initiated.

However, any pending data transfers reads or writes will be completed.

The data bus will tri-state one cycle after the chip is deselected or a write
is initiated.

The IDT71V2557/59 have an on-chip burst counter. In the burst
mode, the IDT71V2557/59 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address ADV/LD = LOW or increment the internal burst counter ADV/LD = HIGH .

The IDT71V2557/59 SRAMs utilize IDT's latest high-performance

CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack TQFP as well as a 119 ball
grid array BGA and a 165 fine pitch ball grid array fBGA .

Pin Description Summary

A0-A17

Address Inputs

CE1, CE2, CE2

Chip Enables

Output Enable

Read/Write Signal

Clock Enable

Input

Synchronous

Input

Synchronous

Input

Asynchronous

Input
Ordering Information

IDT XXXX

Device Type

Power Speed

Package Process/ Temperature Range

Blank Commercial 0°C to +70°C

Industrial -40°C to +85°C

PF 100-pin Plastic Thin Quad Flatpack TQFP BG 119 Ball Grid Array BGA BQ 165 Fine Pitch Ball Grid Array fBGA

Access time tCD in tenths of nanoseconds

IDT71V2557 128Kx36 Flow-Through ZBT SRAM with 2.5V I/O IDT71V2559 256Kx18 Flow-Through ZBT SRAM with 2.5V I/O
* Commercial temperature range only.
4878 drw 12

IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Datasheet Document History
6/30/99 8/23/99
12/31/99 05/02/00
05/26/00 07/26/00 10/25/00

Pg. 5, 6 Pg. 7 Pg. 15 Pg. 21 Pg. 23 Pg. 5, 14, 15, 22 Pg. 5,6

Pg. 5,6,7 Pg. 6 Pg. 21

Pg. 23 Pg. 5-7 Pg. 8 Pg. 23

Pg. 8

CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES 800-345-7015 or 408-727-6116 fax 408-492-8674

The IDT logo is a registered trademark of Integrated Device Technology, Inc.
for Tech Support 800-544-7726, x4033

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT71V2559S85BG8 Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT71V2559S85BG8 637332