IDT71V2546S100PF8

IDT71V2546S100PF8 Datasheet

IDT71V2546S IDT71V2548S IDT71V2546SA IDT71V2548SA

Part	Datasheet
IDT71V2546S100PF8	IDT71V2546S100PF8 (pdf)

Related Parts	Information
IDT71V2546S133PFI	IDT71V2546S133PFI
IDT71V2546S150PFI	IDT71V2546S150PFI
IDT71V2546S150PF8	IDT71V2546S150PF8
IDT71V2546S150PF	IDT71V2546S150PF
IDT71V2546S133PFI8	IDT71V2546S133PFI8
IDT71V2546S133PF8	IDT71V2546S133PF8
IDT71V2546S133PF	IDT71V2546S133PF
IDT71V2546S100PFI8	IDT71V2546S100PFI8
IDT71V2546S100PFI	IDT71V2546S100PFI
IDT71V2546S100PF	IDT71V2546S100PF
IDT71V2546S150PFI8	IDT71V2546S150PFI8
IDT71V2548S133PF	IDT71V2548S133PF
IDT71V2548S150PF	IDT71V2548S150PF
IDT71V2548S150BG8	IDT71V2548S150BG8
IDT71V2548S100PF8	IDT71V2548S100PF8
IDT71V2548S150PF8	IDT71V2548S150PF8
IDT71V2548S133BG8	IDT71V2548S133BG8
IDT71V2548S133BG	IDT71V2548S133BG
IDT71V2548S100BG	IDT71V2548S100BG
IDT71V2548S100BG8	IDT71V2548S100BG8
IDT71V2548S150BG	IDT71V2548S150BG
IDT71V2548S100PF	IDT71V2548S100PF
IDT71V2548S133PF8	IDT71V2548S133PF8

PDF Datasheet Preview
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs IDT71V2546S IDT71V2548S IDT71V2546SA IDT71V2548SA x 128K x 36, 256K x 18 memory configurations x Supports high performance system speed - 150 MHz ns Clock-to-Data Access x ZBTTM Feature - No dead cycles between write and read cycles x Internally synchronized output buffer enable eliminates the need to control OE x Single R/W READ/WRITE control pin x Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications x 4-word burst capability interleaved or linear x Individual byte write BW1 - BW4 control May tie active x Three chip enables for simple depth expansion x 3.3V power supply ±5% , 2.5V I/O Supply VDDQ x Optional Boundary Scan JTAG Interface IEEE1149.1 complaint x Packaged in a JEDEC standard 100-pin plastic thin quad flatpack TQFP , 119 ball grid array BGA and 165 fine pitch ball grid array The IDT71V2546/48 are 3.3V high-speed 4,718,592-bit Mega- bit synchronous SRAMS. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given the name ZBTTM, or Zero Bus Turnaround. Pin Description Summary A0-A17 Address Inputs Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write. The IDT71V2546/48 contain data I/O, address and control signal registers. Output enable is the only asynchronous signal and can be used to disable the outputs at any given time. A Clock Enable CEN pin allows operation of the IDT71V2546/48 to be suspended as long as necessary. All synchronous inputs are ignored when CEN is high and the internal device registers will hold their previous values. There are three chip enable pins CE1, CE2, CE2 that allow the user to deselect the device when desired. If any one of these three are not asserted when ADV/LD is low, no new memory operation can be initiated. However, any pending data transfers reads or writes will be completed. The data bus will tri-state two cycles after chip is deselected or a write is initiated. The IDT71V2546/48 has an on-chip burst counter. In the burst mode, the IDT71V2546/48 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address ADV/LD = LOW or increment the internal burst counter ADV/LD = HIGH . The IDT71V2546/48 SRAMs utilize IDT's latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack TQFP as well as a 119 ball grid array BGA and 165 fine pitch ball grid array fBGA . Input Synchronous CE1, CE2, CE2 Chip Enables Input Synchronous Output Enable Input Asynchronous Read/Write Signal Input Synchronous Clock Enable Input Synchronous BW1, BW2, BW3, BW4 Individual Byte Write Selects Ordering Information IDT XXXX Device Type Power Speed Package Process/ Temperature Range Blank Commercial 0°C to +70°C Industrial -40°C to +85°C PF** 100-pin Plastic Thin Quad Flatpack TQFP BG 119 Ball Grid Array BGA BQ 165 Fine Pitch Ball Grid Array fBGA 150* 133 Clock Frequency in Megahertz 100 Standard Power SA Standard Power with JTAG Interface IDT71V2546 128Kx36 Pipelined ZBT SRAM with 2.5V I/O IDT71V2548 256Kx18 Pipelined ZBT SRAM with 2.5V I/O 5294 drw 12 Available in commercial range only * JTAG SA version is not available with 100-pin TQFP package IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Datasheet Document History 12/31/99 03/04/00 05/02/00 05/26/00 07/26/00 10/25/00 05/20/02 Pg. 1,14, 15,22 Pg. 5,6 Pg. 5,6,7 Pg. 6 Pg. 21 Pg. 23 Pg. 5-8 Pg. 8 Pg. 23 Pg. 8 Pg. 1-8,15,22,23, Created preliminary datasheet from 71V2556 and 71V2558 datasheets. Changed tCDC, t tCLZ, andtCHZ minimums from 1.0ns to 1.5ns. Add 150 MHz speed grade offering Insert clarification note to Recommended Operating Temperature and Absolute Max Ratings tables Clarify note onTQFP and BGA pin configurations corrected typo in pinout Add BGA capacitance table Add 100 pin TQFP Package Diagram Outline Add new package offering, 13 x 15mm 165 fBGA Correct 119 BGA Package Diagram Outline Add ZZ, sleep mode refernce note to BG119, PK100 and BQ165 pinouts Update BQ165 pinout Update BG119 Package Diagram Outline dimensions Remove Preliminary status from datasheet Add reference note to pin N5 on BQ165, reserved for JTAG pin TRST Added JTAG "SA" version functionality and updated ZZ pin descriptions and notes CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES 800-345-7015 or 408-727-6116 fax 408-492-8674 for Tech Support 800-544-7726, x4033 The IDT logo is a registered trademark of Integrated Device Technology, Inc. ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.

PDF Datasheet Preview

128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs

IDT71V2546S IDT71V2548S IDT71V2546SA IDT71V2548SA
x 128K x 36, 256K x 18 memory configurations x Supports high performance system speed - 150 MHz
ns Clock-to-Data Access x ZBTTM Feature - No dead cycles between write and read
cycles x Internally synchronized output buffer enable eliminates the
need to control OE x Single R/W READ/WRITE control pin x Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications x 4-word burst capability interleaved or linear x Individual byte write BW1 - BW4 control May tie active x Three chip enables for simple depth expansion x 3.3V power supply ±5% , 2.5V I/O Supply VDDQ x Optional Boundary Scan JTAG Interface IEEE1149.1
complaint x Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack TQFP , 119 ball grid array BGA and 165 fine
pitch ball grid array

The IDT71V2546/48 are 3.3V high-speed 4,718,592-bit Mega-
bit synchronous SRAMS. They are designed to eliminate dead bus cycles
when turning the bus around between reads and writes, or writes and
reads. Thus, they have been given the name ZBTTM, or Zero Bus

Turnaround.

Pin Description Summary

A0-A17

Address Inputs

Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write.

The IDT71V2546/48 contain data I/O, address and control signal registers. Output enable is the only asynchronous signal and can be used to disable the outputs at any given time.

A Clock Enable CEN pin allows operation of the IDT71V2546/48 to be suspended as long as necessary. All synchronous inputs are ignored when CEN is high and the internal device registers will hold their previous values.

There are three chip enable pins CE1, CE2, CE2 that allow the user to deselect the device when desired. If any one of these three are not asserted when ADV/LD is low, no new memory operation can be initiated. However, any pending data transfers reads or writes will be completed. The data bus will tri-state two cycles after chip is deselected or a write is initiated.

The IDT71V2546/48 has an on-chip burst counter. In the burst mode, the IDT71V2546/48 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address ADV/LD = LOW or increment the internal burst counter ADV/LD = HIGH .

The IDT71V2546/48 SRAMs utilize IDT's latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack TQFP as well as a 119 ball grid array BGA and 165 fine pitch ball grid array fBGA .

Input

Synchronous

CE1, CE2, CE2

Chip Enables

Input

Synchronous

Output Enable

Input

Asynchronous

Read/Write Signal

Input

Synchronous

Clock Enable

Input

Synchronous

BW1, BW2, BW3, BW4

Individual Byte Write Selects
Ordering Information

IDT XXXX

Device Type

Power Speed

Package Process/ Temperature Range

Blank Commercial 0°C to +70°C

Industrial -40°C to +85°C

PF** 100-pin Plastic Thin Quad Flatpack TQFP BG 119 Ball Grid Array BGA BQ 165 Fine Pitch Ball Grid Array fBGA
150*
133 Clock Frequency in Megahertz 100

Standard Power

SA Standard Power with JTAG Interface

IDT71V2546 128Kx36 Pipelined ZBT SRAM with 2.5V I/O IDT71V2548 256Kx18 Pipelined ZBT SRAM with 2.5V I/O
5294 drw 12 *Available in commercial range only ** JTAG SA version is not available with 100-pin TQFP package

IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Datasheet Document History
12/31/99 03/04/00 05/02/00
05/26/00 07/26/00 10/25/00 05/20/02

Pg. 1,14, 15,22 Pg. 5,6

Pg. 5,6,7 Pg. 6 Pg. 21

Pg. 23 Pg. 5-8 Pg. 8 Pg. 23

Pg. 8 Pg. 1-8,15,22,23,

Created preliminary datasheet from 71V2556 and 71V2558 datasheets. Changed tCDC, t tCLZ, andtCHZ minimums from 1.0ns to 1.5ns. Add 150 MHz speed grade offering

Insert clarification note to Recommended Operating Temperature and Absolute Max Ratings tables Clarify note onTQFP and BGA pin configurations corrected typo in pinout Add BGA capacitance table Add 100 pin TQFP Package Diagram Outline Add new package offering, 13 x 15mm 165 fBGA Correct 119 BGA Package Diagram Outline Add ZZ, sleep mode refernce note to BG119, PK100 and BQ165 pinouts Update BQ165 pinout Update BG119 Package Diagram Outline dimensions Remove Preliminary status from datasheet Add reference note to pin N5 on BQ165, reserved for JTAG pin TRST Added JTAG "SA" version functionality and updated ZZ pin descriptions and notes

CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES 800-345-7015 or 408-727-6116 fax 408-492-8674
for Tech Support 800-544-7726, x4033

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT71V2546S100PF8 Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT71V2546S100PF8 637328