IDT71P74804S167BQ8

IDT71P74804S167BQ8 Datasheet

IDT71P74804 IDT71P74604

Part	Datasheet
IDT71P74804S167BQ8	IDT71P74804S167BQ8 (pdf)

Related Parts	Information
IDT71P74804S167BQ	IDT71P74804S167BQ
IDT71P74604S200BQG	IDT71P74604S200BQG
IDT71P74604S167BQ	IDT71P74604S167BQ
IDT71P74604S167BQ8	IDT71P74604S167BQ8
IDT71P74604S167BQG	IDT71P74604S167BQG
IDT71P74604S167BQG8	IDT71P74604S167BQG8
IDT71P74604S200BQ	IDT71P74604S200BQ
IDT71P74604S200BQ8	IDT71P74604S200BQ8
IDT71P74804S200BQ	IDT71P74804S200BQ
IDT71P74804S250BQG8	IDT71P74804S250BQG8
IDT71P74804S250BQG	IDT71P74804S250BQG
IDT71P74804S250BQ8	IDT71P74804S250BQ8
IDT71P74804S250BQ	IDT71P74804S250BQ
IDT71P74804S200BQG8	IDT71P74804S200BQG8
IDT71P74604S250BQG	IDT71P74604S250BQG
IDT71P74804S200BQ8	IDT71P74804S200BQ8
IDT71P74604S200BQG8	IDT71P74604S200BQG8
IDT71P74804S167BQG8	IDT71P74804S167BQG8
IDT71P74804S167BQG	IDT71P74804S167BQG
IDT71P74604S250BQG8	IDT71P74604S250BQG8
IDT71P74604S250BQ8	IDT71P74604S250BQ8
IDT71P74604S250BQ	IDT71P74604S250BQ
IDT71P74804S200BQG	IDT71P74804S200BQG

PDF Datasheet Preview
18Mb Pipelined QDR II SRAM Burst of 4 IDT71P74804 IDT71P74604 • 18Mb Density 1Mx18, 512kx36 • Separate, Independent Read and Write Data Ports - Supports concurrent transactions • Dual Echo Clock Output • 4-Word Burst on all SRAM accesses • Multiplexed Address Bus One Read or One Write request per clock cycle • DDR Double Data Rate Data Bus - Four word burst data per two clock cycles on each port - Four word transfers per clock cycle • Depth expansion through Control Logic • HSTL 1.5V inputs that can be scaled to receive signals from 1.4V to 1.9V. • Scalable output drivers - Can drive HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V. - Output Impedance adjustable from to • 1.8V Core Voltage VDD • 165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package • JTAG Interface The IDT QDRIITM Burst of four SRAMs are high-speed synchronous memories with independent, double-data-rate DDR , read and write data ports. This scheme allows simultaneous read and write access for the maximum device throughput, with four data items passed with each read or write. Four data word transfers occur per clock cycle, providing quad-data-rate QDR performance. Comparing this with standard SRAM common I/O CIO , single data rate SDR devices, a four to one increase in data access is achieved at equivalent clock speeds. Considering that QDRII allows clock speeds in excess of standard SRAM devices, the throughput can be increased well beyond four to one in most applications. Using independent ports for read and write data access, simplifies system design by eliminating the need for bi-directional buses. All buses associated with the QDRII are unidirectional and can be optimized for signal integrity at very high bus speeds. The QDRII has scalable output impedance on its data output bus and echo clocks, allowing the user to tune the bus for low noise and high performance. The QDRII has a single SDR address bus with read addresses and write addresses multiplexed. The read and write addresses interleave with each occurring a maximum of every other cycle. In the event that no operation takes place on a cycle, the subsequest cycle may begin with either a read or write. During write operations, the writing of individual bytes may be blocked through the use of byte write control signals. Functional Block Diagram WRITE/READ DECODE SENSE AMPS OUTPUT SELECT OUTPUT REG OUTPUT SELECT Note1 DATA REG Note2 ADD Note2 REG Note3 CTRL LOGIC WRITE DRIVER 18M MEMORY ARRAY Note 4 Note 4 Note1 SELECT OUTPUT CONTROL Notes 1 Represents 18 data signal lines for x18 and 36 signal lines for x36. 2 Represents 18 address signal lines for x18 and 17 address signal lines for x36. 3 Represents 2 signal lines for x18 and 4 signal lines for x36. 4 Represents 36 signal lines for x18 and 72 signal lines for x36. 6111 drw16 SEPTEMBER 2008 2008 Integrated Device Technology, Inc. QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. DSC-6111/02 IDT71P74804 1M x 18-Bit 71P74604 512K x 36-Bit 18 Mb QDR II SRAM Burst of 4 The QDRII has echo clocks, which provide the user with a clock that is precisely timed to the data output, and tuned with matching impedance and signal quality. The user can use the echo clock for downstream clocking of the data. Echo clocks eliminate the need for the user to produce alternate clocks with precise timing, positioning, and signal qualities to guarantee data capture. Since the echo clocks are generated by the same source that drives the data output, the relationship to the data is not significantly affected by voltage, temperature and process, as would be the case if the clock were generated by an outside source. All interfaces of the QDRII SRAM are HSTL, allowing speeds beyond SRAM devices that use any form of TTL interface. The interface can be scaled to higher voltages up to 1.9V to interface with 1.8V systems if necessary. The device has a VDDQ and a separate Vref, allowing the user to designate the interface operational voltage, independent of the device core voltage of 1.8V VDD. The output impedance control allows the user to adjust the drive strength to adapt to a wide range of loads and transmission lines. The device is capable of sustaining full bandwidth on both the input and output ports simultaneously. All data is in four word bursts, with addressing capability to the burst level. Clocking The QDRII SRAM has two sets of input clocks, namely the K, K clocks and the C, C clocks. In addition, the QDRII has an output “echo” clock, CQ, CQ. The K and K clocks are the primary device input clocks. The K clock is, used to clock in the control signals R, W and BWx , the address, first and third words of the data burst during a write operation. The K clock is used to clock in the control signals BWx and the second and fourth words of the data burst during a write operation. The K and K clocks are also used internally by the SRAM. In the event that the user disables the C and C clocks, the K and K clocks will be used to clock the data out of the output register and generate the echo clocks. The C and C clocks may be used to clock the data out of the output register during read operations and to generate the echo clocks. C and C must be presented to the SRAM within the timing tolerances. The output data from the QDRII will be closely aligned to the C and C input, through the use of an internal DLL. When C is presented to the QDRII SRAM, the DLL will have already internally clocked the first data word to arrive at the device output simultaneously with the arrival of the C clock. The C and second data word of the burst will also correspond. The third and fourth data words will follow on the next clock cycle of C and C, respectively. Single Clock Mode The QDRII SRAM may be operated with a single clock pair. C and C may be disabled by tying both signals high, forcing the outputs and echo clocks to be controlled instead by the K and K clocks. DLL Operation The DLL in the output structure of the QDRII SRAM can be used to Ordering Information Commercial Temperature Range CORPORATE HEADQUARTERS for SALES: for Tech Support: 6024 Silver Creek Valley Road 800-345-7015 or San Jose, CA 95138 408-284-8200 800-345-7015 fax 408-284-2775 “QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “ IDT71P74804 1M x 18 x -Bit 71P74604 512K x 36-Bit 18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range DATE 07/20/05 12/07/07 09/23/08 PAGES p. 1-22 p. 1-22 p. 12 DESCRIPTION Released Final datasheet Removed 71P4204 and 71P4104 speed grades. Change 250MHz and 200MHz max tKHKH from and to 8.40ns.

PDF Datasheet Preview

18Mb Pipelined QDR II SRAM Burst of 4

IDT71P74804 IDT71P74604
• 18Mb Density 1Mx18, 512kx36
• Separate, Independent Read and Write Data Ports
- Supports concurrent transactions
• Dual Echo Clock Output
• 4-Word Burst on all SRAM accesses
• Multiplexed Address Bus One Read or One Write request per
clock cycle
• DDR Double Data Rate Data Bus
- Four word burst data per two clock cycles on each port - Four word transfers per clock cycle
• Depth expansion through Control Logic
• HSTL 1.5V inputs that can be scaled to receive signals from 1.4V to 1.9V.
• Scalable output drivers - Can drive HSTL, 1.8V TTL or any voltage level from 1.4V
to 1.9V. - Output Impedance adjustable from to
• 1.8V Core Voltage VDD
• 165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package
• JTAG Interface

The IDT QDRIITM Burst of four SRAMs are high-speed synchronous memories with independent, double-data-rate DDR , read and write data ports. This scheme allows simultaneous read and write access for the maximum device throughput, with four data items passed with each read or write. Four data word transfers occur per clock cycle, providing quad-data-rate QDR performance. Comparing this with standard SRAM common I/O CIO , single data rate SDR devices, a four to one increase in data access is achieved at equivalent clock speeds. Considering that QDRII allows clock speeds in excess of standard SRAM devices, the throughput can be increased well beyond four to one in most applications.

Using independent ports for read and write data access, simplifies system design by eliminating the need for bi-directional buses. All buses associated with the QDRII are unidirectional and can be optimized for signal integrity at very high bus speeds. The QDRII has scalable output impedance on its data output bus and echo clocks, allowing the user to tune the bus for low noise and high performance.

The QDRII has a single SDR address bus with read addresses and write addresses multiplexed. The read and write addresses interleave with each occurring a maximum of every other cycle. In the event that no operation takes place on a cycle, the subsequest cycle may begin with either a read or write. During write operations, the writing of individual bytes may be blocked through the use of byte write control signals.

Functional Block Diagram

WRITE/READ DECODE SENSE AMPS

OUTPUT SELECT OUTPUT REG

OUTPUT SELECT

Note1 DATA REG

Note2

ADD Note2 REG

Note3

CTRL LOGIC

WRITE DRIVER
18M MEMORY

ARRAY

Note 4 Note 4

Note1

SELECT OUTPUT CONTROL

Notes 1 Represents 18 data signal lines for x18 and 36 signal lines for x36. 2 Represents 18 address signal lines for x18 and 17 address signal lines for x36. 3 Represents 2 signal lines for x18 and 4 signal lines for x36. 4 Represents 36 signal lines for x18 and 72 signal lines for x36.
6111 drw16

SEPTEMBER 2008
2008 Integrated Device Technology, Inc. QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.

DSC-6111/02

IDT71P74804 1M x 18-Bit 71P74604 512K x 36-Bit 18 Mb QDR II SRAM Burst of 4

The QDRII has echo clocks, which provide the user with a clock that is precisely timed to the data output, and tuned with matching impedance and signal quality. The user can use the echo clock for downstream clocking of the data. Echo clocks eliminate the need for the user to produce alternate clocks with precise timing, positioning, and signal qualities to guarantee data capture. Since the echo clocks are generated by the same source that drives the data output, the relationship to the data is not significantly affected by voltage, temperature and process, as would be the case if the clock were generated by an outside source.

All interfaces of the QDRII SRAM are HSTL, allowing speeds beyond SRAM devices that use any form of TTL interface. The interface can be scaled to higher voltages up to 1.9V to interface with 1.8V systems if necessary. The device has a VDDQ and a separate Vref, allowing the user to designate the interface operational voltage, independent of the device core voltage of 1.8V VDD. The output impedance control allows the user to adjust the drive strength to adapt to a wide range of loads and transmission lines.

The device is capable of sustaining full bandwidth on both the input and output ports simultaneously. All data is in four word bursts, with addressing capability to the burst level. Clocking

The QDRII SRAM has two sets of input clocks, namely the K, K clocks and the C, C clocks. In addition, the QDRII has an output “echo” clock, CQ, CQ.

The K and K clocks are the primary device input clocks. The K clock is, used to clock in the control signals R, W and BWx , the address, first and third words of the data burst during a write operation. The K clock is used to clock in the control signals BWx and the second and fourth words of the data burst during a write operation. The K and K clocks are also used internally by the SRAM. In the event that the user disables the C and C clocks, the K and K clocks will be used to clock the data out of the output register and generate the echo clocks.

The C and C clocks may be used to clock the data out of the output register during read operations and to generate the echo clocks. C and C must be presented to the SRAM within the timing tolerances. The output data from the QDRII will be closely aligned to the C and C input, through the use of an internal DLL. When C is presented to the QDRII SRAM, the DLL will have already internally clocked the first data word to arrive at the device output simultaneously with the arrival of the C clock. The C and second data word of the burst will also correspond. The third and fourth data words will follow on the next clock cycle of C and C,
respectively.

Single Clock Mode The QDRII SRAM may be operated with a single clock pair. C and

C may be disabled by tying both signals high, forcing the outputs and echo clocks to be controlled instead by the K and K clocks.

DLL Operation The DLL in the output structure of the QDRII SRAM can be used to
Ordering Information

Commercial Temperature Range

CORPORATE HEADQUARTERS for SALES:
for Tech Support:
6024 Silver Creek Valley Road
800-345-7015 or

San Jose, CA 95138
408-284-8200
800-345-7015
fax 408-284-2775
“QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “

IDT71P74804 1M x 18 x -Bit 71P74604 512K x 36-Bit 18 Mb QDR II SRAM Burst of 4

Commercial Temperature Range

DATE 07/20/05 12/07/07 09/23/08

PAGES p. 1-22 p. 1-22 p. 12

DESCRIPTION Released Final datasheet Removed 71P4204 and 71P4104 speed grades. Change 250MHz and 200MHz max tKHKH from and to 8.40ns.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT71P74804S167BQ8 Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT71P74804S167BQ8 637325