IDT71P73204 IDT71P73104 IDT71P73804 IDT71P73604
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IDT71P73804S250BQ |
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IDT71P73604S250BQ8 |
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IDT71P73604S200BQ |
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IDT71P73604S167BQ8 |
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IDT71P73804S200BQ |
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18Mb Pipelined DDR II SRAM Burst of 4 IDT71P73204 IDT71P73104 IDT71P73804 IDT71P73604 18Mb Density 2Mx8, 2Mx9, 1Mx18, 512Kx36 Common Read and Write Data Port Dual Echo Clock Output 4-Word Burst on all SRAM accesses MultiplexedAddress Bus - One Read or One Write request per two clock cycles. DDR Double Data Rate Data Bus - Four word bursts data per two clock cycles Depth expansion through Control Logic HSTL 1.5V inputs that can be scaled to receive signals from 1.4V to 1.9V. Scalable output drivers - Can drive HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V. - Output Impedance adjustable from 35 ohms to 70 ohms 1.8V Core Voltage VDD JTAG Interface 165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package The IDT DDRIITM Burst of four SRAMs are high-speed synchronous memories with a double-data-rate DDR , bidirectional data port. This scheme allows maximization on the bandwidth on the data bus by passing two data items per clock cycle. The address bus operates at less than single data rate speeds,allowing the user to fan out addresses and ease system design while maintaining maximum performance on data transfers. The DDRII has scalable output impedance on its data output bus and echo clocks, allowing the user to tune the bus for low noise and high performance. All interfaces of the DDRII SRAM are HSTL, allowing speeds beyond SRAM devices that use any form of TTL interface. The interface can be scaled to higher voltages up to 1.9V to interface with 1.8V systems if necessary. The device has a VDDQ and a separate Vref, allowing the user to designate the interface operational voltage, independent of the device core voltage of 1.8V VDD. The output impedance control allows the user to adjust the drive strength to adapt to a wide range of loads and transmission lines. Functional Block Diagram WRITE/READ DECODE SENSE AMPS OUTPUT REG OUTPUT SELECT DATA REG Note2 SA SA0 ADD REG Note2 RW BWx Note3 CTRL LOGIC Note1 WRITE DRIVER 18M MEMORY ARRAY Note4 Note4 Note1 DQ SELECT OUTPUT CONTROL Notes 6431 drw 16 1 Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36 2 Represents 19 address signal lines for x8 and x9, 20 address signal lines for x18, and 19 address signal lines for x36. 3 Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a “nibble write” and there are 2 signal lines. 4 Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36. JULY 2005 2005 Integrated Device Technology, Inc. “QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.“ DSC-6431/00 IDT71P73204 2M x 8-Bit , 71P73104 2M x 9-Bit , 71P73804 1M x 18-Bit 71P73604 512K x 36-Bit Ordering Information IDT 71P73XXX X Device Power Speed Package Type BQ 165 Fine Pitch Ball Grid Array fBGA Clock Frequency in MegaHertz IDT71P73204 2M x 8 DDR II SRAM Burst of 4 IDT71P73104 2M x 9 DDR II SRAM Burst of 4 IDT71P73804 1M x 18 DDR II SRAM Burst of 4 IDT71P73604 512K x 36 DDR II SRAM Burst of 4 6431 drw 15 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support 800-345-7015 “QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “ IDT71P73204 2M x 8-Bit , 71P73104 2M x 9-Bit , 71P73804 1M x 18 x -Bit 71P73604 512K x 36-Bit 18 Mb DDR II SRAM Burst of 4 Commercial Temperature Range 07/29/05 PAGES p. 1-24 DESCRIPTION Released Final datasheet |
More datasheets: RSVS2418BK1 | RSUS1931BK1 | RSVS1931CG1 | KP120T | LTDL-RX16S01B | IDT71P73804S167BQ | IDT71P73604S167BQ | IDT71P73804S250BQ8 | IDT71P73804S250BQ | IDT71P73804S200BQ8 |
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