IDT71P72804S200BQ

IDT71P72804S200BQ Datasheet

IDT71P72804 IDT71P72604

Part	Datasheet
IDT71P72804S200BQ	IDT71P72804S200BQ (pdf)

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PDF Datasheet Preview
18Mb Pipelined QDR II SRAM Burst of 2 IDT71P72804 IDT71P72604 18Mb Density 1Mx18, 512kx36 Separate, Independent Read and Write Data Ports - Supports concurrent transactions Dual Echo Clock Output 2-Word Burst on all SRAM accesses DDR Double Data Rate Multiplexed Address Bus - One Read and One Write request per clock cycle DDR Double Data Rate Data Buses - Two word burst data per clock on each port - Four word transfers per clock cycle 2 word bursts on 2 ports Depth expansion through Control Logic HSTL 1.5V inputs that can be scaled to receive signals from 1.4V to 1.9V. Scalable output drivers - Can drive HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V. - Output Impedance adjustable from 35 ohms to 70 ohms Commercial and Industrial Temperature Ranges 1.8V Core Voltage VDD 165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package JTAG Interface The IDT QDRIITM Burst of two SRAMs are high-speed synchronous memories with independent, double-data-rate DDR , read and write data ports. This scheme allows simultaneous read and write access for the maximum device throughput, with two data items passed with each read or write. Four data word transfers occur per clock cycle, providing quad-data-rate QDR performance. Comparing this with standard SRAM common I/O CIO , single data rate SDR devices, a four to one increase in data access is achieved at equivalent clock speeds. Considering that QDRII allows clock speeds in excess of standard SRAM devices, the throughput can be increased well beyond four to one in most applications. Using independent ports for read and write data access, simplifies system design by eliminating the need for bi-directional buses. All buses associated with the QDRII are unidirectional and can be optimized for signal integrity at very high bus speeds. The QDRII has scalable output impedance on its data output bus and echo clocks, allowing the user to tune the bus for low noise and high performance. The QDRII has a single DDR address bus with multiplexed read and write addresses. All read addresses are received on the first half of the clock cycle and all write addresses are received on the second half of the clock cycle. The read and write enables are received on the first half of the clock cycle. The byte and nibble write signals are received on both halves of the clock cycle simultaneously with the data they are controlling on the data input bus. Functional Block Diagram Note1 D DATA REG DATA REG Note1 SA Note2 ADD REG Note2 R W BWx CTRL Note3 LOGIC WRITE DRIVER 18M MEMORY ARRAY Note4 Note4 Note1 Q WRITE/READ DECODE SENSE AMPS OUTPUT REG OUTPUT SELECT SELECT OUTPUT CONTROL Notes 1 Represents 18 signal lines for x18, and 36 signal lines for x36 2 Represents 19 address signal lines for x18, and 18 address signal lines for x36. 3 Represents 2 signal lines for x18, and 4r signal lines for x36. 4 Represents 36 signal lines for x18, and 72 signal lines for x36. 6109 drw 16 OCTOBER 2008 2005 Integrated Device Technology, Inc. QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. DSC-6109/0A 71P72804 1M x 18-Bit 71P72604 512K x 36-Bit 18 Mb QDR II SRAM Burst of 2 Commercial and IndustrialTemperature Range The QDRII has echo clocks, which provide the user with a clock that is precisely timed to the data output, and tuned with matching impedance and signal quality. The user can use the echo clock for downstream clocking of the data. Echo clocks eliminate the need for the user to produce alternate clocks with precise timing, positioning, and signal qualities to guarantee data capture. Since the echo clocks are generated by the same source that drives the data output, the relationship to the data is not significantly affected by voltage, temperature and process, as would be the case if the clock were generated by an outside source. Ordering Information 71P72XXX S Device Power Type XXX Speed BQ Package Process Temperature Range Commercial and IndustrialTemperature Range Blank I G Commercial 0oC to +70oC Industrial -40oC to +85oC Restricted Hazardous Substance Device 165 Fine Pitch Ball Grid Array fBGA 250 1,2 200 167 Clock Frequency in MegaHertz IDT71P72804 1M x 18 QDR II SRAM Burst of 2 IDT71P72604 512K x 36 QDR II SRAM Burst of 2 Notes 1 The 250MHz speed grade is not available in the 512K x36-bit option. 2 Industrial temperature range is not available for the 250MHz speed grade. 6109 drw 15 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support 408-284-4532 “QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “ IDT71P72204 2M x 8-Bit , 71P72104 2M x 9-Bit , 71P72804 1M x 18 x -Bit 71P72604 512K x 36-Bit 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range DATE 07/20/05 04/21/06 10/13/08 PAGES p.1-22 p.1-3,7-9 12,15,20 p. 7,11,17 p.1,7,9,12,20 p.20 p.20 DESCRIPTION Released Final datasheet Removed x8 and x9 information from the datasheet. Clarified Max VDDQ equals VDD. Added Industrial temperature to the datasheet. Added Green to the datasheet “Restricted hazardous substance device” Removed "IDT" from orderable part number

PDF Datasheet Preview

18Mb Pipelined QDR II SRAM Burst of 2

IDT71P72804 IDT71P72604
18Mb Density 1Mx18, 512kx36 Separate, Independent Read and Write Data Ports
- Supports concurrent transactions Dual Echo Clock Output 2-Word Burst on all SRAM accesses DDR Double Data Rate Multiplexed Address Bus
- One Read and One Write request per clock cycle DDR Double Data Rate Data Buses
- Two word burst data per clock on each port - Four word transfers per clock cycle 2 word bursts
on 2 ports Depth expansion through Control Logic HSTL 1.5V inputs that can be scaled to receive signals
from 1.4V to 1.9V. Scalable output drivers
- Can drive HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V.
- Output Impedance adjustable from 35 ohms to 70 ohms

Commercial and Industrial Temperature Ranges 1.8V Core Voltage VDD 165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package JTAG Interface

The IDT QDRIITM Burst of two SRAMs are high-speed synchronous memories with independent, double-data-rate DDR , read and write data ports. This scheme allows simultaneous read and write access for the maximum device throughput, with two data items passed with each read or write. Four data word transfers occur per clock cycle, providing quad-data-rate QDR performance. Comparing this with standard SRAM common I/O CIO , single data rate SDR devices, a four to one increase in data access is achieved at equivalent clock speeds. Considering that QDRII allows clock speeds in excess of standard SRAM devices, the throughput can be increased well beyond four to one in most applications.

Using independent ports for read and write data access, simplifies system design by eliminating the need for bi-directional buses. All buses associated with the QDRII are unidirectional and can be optimized for signal integrity at very high bus speeds. The QDRII has scalable output impedance on its data output bus and echo clocks, allowing the user to tune the bus for low noise and high performance.

The QDRII has a single DDR address bus with multiplexed read and write addresses. All read addresses are received on the first half of the clock cycle and all write addresses are received on the second half of the clock cycle. The read and write enables are received on the first half of the clock cycle. The byte and nibble write signals are received on both halves of the clock cycle simultaneously with the data they are controlling on the data input bus.

Functional Block Diagram

Note1 D

DATA REG

DATA REG

Note1

SA Note2

ADD REG

Note2

R W BWx

CTRL Note3 LOGIC

WRITE DRIVER
18M MEMORY

ARRAY

Note4

Note4

Note1 Q

WRITE/READ DECODE SENSE AMPS OUTPUT REG

OUTPUT SELECT

SELECT OUTPUT CONTROL

Notes 1 Represents 18 signal lines for x18, and 36 signal lines for x36 2 Represents 19 address signal lines for x18, and 18 address signal lines for x36. 3 Represents 2 signal lines for x18, and 4r signal lines for x36. 4 Represents 36 signal lines for x18, and 72 signal lines for x36.
6109 drw 16

OCTOBER 2008
2005 Integrated Device Technology, Inc. QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.

DSC-6109/0A
71P72804 1M x 18-Bit 71P72604 512K x 36-Bit 18 Mb QDR II SRAM Burst of 2

Commercial and IndustrialTemperature Range

The QDRII has echo clocks, which provide the user with a clock that is precisely timed to the data output, and tuned with matching impedance and signal quality. The user can use the echo clock for downstream clocking of the data. Echo clocks eliminate the need for the user to produce alternate clocks with precise timing, positioning, and signal qualities to guarantee data capture. Since the echo clocks are generated by the same source that drives the data output, the relationship to the data is not significantly affected by voltage, temperature and process, as would be the case if the clock were generated by an outside source.
Ordering Information
71P72XXX S

Device Power Type

XXX Speed

BQ Package

Process Temperature

Range

Commercial and IndustrialTemperature Range

Blank I G

Commercial 0oC to +70oC Industrial -40oC to +85oC

Restricted Hazardous Substance Device
165 Fine Pitch Ball Grid Array fBGA
250 1,2
200 167

Clock Frequency in MegaHertz

IDT71P72804 1M x 18 QDR II SRAM Burst of 2 IDT71P72604 512K x 36 QDR II SRAM Burst of 2

Notes 1 The 250MHz speed grade is not available in the 512K x36-bit option. 2 Industrial temperature range is not available for the 250MHz speed grade.
6109 drw 15

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775
for Tech Support 408-284-4532
“QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “

IDT71P72204 2M x 8-Bit , 71P72104 2M x 9-Bit , 71P72804 1M x 18 x -Bit 71P72604 512K x 36-Bit
18 Mb QDR II SRAM Burst of 2

Commercial Temperature Range

DATE 07/20/05 04/21/06
10/13/08

PAGES p.1-22 p.1-3,7-9
12,15,20 p. 7,11,17 p.1,7,9,12,20 p.20 p.20

DESCRIPTION Released Final datasheet Removed x8 and x9 information from the datasheet.

Clarified Max VDDQ equals VDD. Added Industrial temperature to the datasheet. Added Green to the datasheet “Restricted hazardous substance device” Removed "IDT" from orderable part number

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT71P72804S200BQ Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT71P72804S200BQ 637323