IDT71P71604S200BQ8

IDT71P71604S200BQ8 Datasheet

Information IDT71P71204 IDT71P71104 IDT71P71804

Part	Datasheet
IDT71P71604S200BQ8	IDT71P71604S200BQ8 (pdf)

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Advance 18Mb Pipelined DDR II SRAM Burst of 2 Information IDT71P71204 IDT71P71104 IDT71P71804 x 18Mb Density 2Mx8, 2Mx9, 1Mx18, 512kx36 x Common Read and Write Data Port x Dual Echo Clock Output x 2-Word Burst on all SRAM accesses x Multiplexed Address Bus - One Read or One Write request per clock cycle x DDR Double Data Rate Data Bus - Two word bursts data per clock x Depth expansion through Control Logic x HSTL 1.5V inputs that can be scaled to receive signals from 1.4V to 1.9V. x Scalable output drivers - Can drive HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V. - Output Impedance adjustable from 35 ohms to 70 ohms x 1.8V Core Voltage VDD x 165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package x JTAG Interface IDT71P71604 The IDT DDRIITM Burst of two SRAMs are high-speed synchronous memories with a double-data-rate DDR , bidirectional data port. This scheme allows maximization of the bandwidth on the data bus by passing two data items per clock cycle. The address bus operates at single data rate speeds, allowing the user to fan out addresses and ease system design while maintaining maximum performance on data transfers. The DDRII has scalable output impedance on its data output bus and echo clocks, allowing the user to tune the bus for low noise and high performance. All interfaces of the DDRII SRAM are HSTL, allowing speeds beyond SRAM devices that use any form of TTL interface. The interface can be scaled to higher voltages up to 1.9V to interface with 1.8V systems if necessary. The device has a VDDQ and a separate Vref, allowing the user to designate the interface operational voltage, independent of the device core voltage of 1.8V VDD. The output impedance control allows the user to adjust the drive strength to adapt to a wide range of loads and transmission lines. Clocking The DDRII SRAM has two sets of input clocks, namely the K, K clocks and the C, C clocks. In addition, the DDRII has an output “echo” clock, CQ, CQ. The K and K clocks are the primary device input clocks. The K clock is used to clock in the control signals LD, R/W and BWx or NWx , the address, and the first word of the data burst during a write operation. Functional Block Diagram WRITE/READ DECODE SENSE AMPS OUTPUT REG OUTPUT SELECT DATA REG Note2 SA SA0 ADD REG Note2 LD R/W BWx Note3 CTRL LOGIC Note 1 WRITE DRIVER 18M MEMORY ARRAY Note1 Note4 Note1 DQ SELECT OUTPUT CONTROL Notes 6112 drw 16 1 Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36 2 Represents 20 address signal lines for x8 and x9, 19 address signal lines for x18, and 18 address signal lines for x36. 3 Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a “nibble write” and there are 2 signal lines. 4 Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36. Ordering Information IDT 71P71XXX Device Type Power Speed BQ Package 165 Fine Pitch Ball Grid Array fBGA 333 300 250 Clock Frequency in MegaHertz 200 167 IDT71P71204 2M x 8 DDR II SRAM Burst of 2 IDT71P71104 2M x 9 DDR II SRAM Burst of 2 IDT71P71804 1M x 18 DDR II SRAM Burst of 2 IDT71P71604 512K x 36 DDR II SRAM Burst of 2 6112 drw 15 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES 800-345-7015 or 408-727-6116 fax 408-492-8674 for Tech Support 800-544-7726 “QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “ IDT71P71204 2M x 8-Bit , 71P71104 2M x 9-Bit , 71P71804 1M x 18 x -Bit 71P71604 512K x 36-Bit Advance Information 18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range DATE 05/31/04 PAGES DESCRIPTION 1-23 Initial Advance Information Data Sheet Release

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Advance
18Mb Pipelined DDR II SRAM Burst of 2

Information IDT71P71204 IDT71P71104 IDT71P71804
x 18Mb Density 2Mx8, 2Mx9, 1Mx18, 512kx36 x Common Read and Write Data Port x Dual Echo Clock Output x 2-Word Burst on all SRAM accesses x Multiplexed Address Bus
- One Read or One Write request per clock cycle x DDR Double Data Rate Data Bus
- Two word bursts data per clock x Depth expansion through Control Logic x HSTL 1.5V inputs that can be scaled to receive signals
from 1.4V to 1.9V. x Scalable output drivers
- Can drive HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V.
- Output Impedance adjustable from 35 ohms to 70 ohms
x 1.8V Core Voltage VDD x 165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package x JTAG Interface

IDT71P71604

The IDT DDRIITM Burst of two SRAMs are high-speed synchronous memories with a double-data-rate DDR , bidirectional data port. This scheme allows maximization of the bandwidth on the data bus by passing two data items per clock cycle. The address bus operates at single data rate speeds, allowing the user to fan out addresses and ease system design while maintaining maximum performance on data transfers.

The DDRII has scalable output impedance on its data output bus and echo clocks, allowing the user to tune the bus for low noise and high performance.

All interfaces of the DDRII SRAM are HSTL, allowing speeds beyond SRAM devices that use any form of TTL interface. The interface can be scaled to higher voltages up to 1.9V to interface with 1.8V systems if necessary. The device has a VDDQ and a separate Vref, allowing the user to designate the interface operational voltage, independent of the device core voltage of 1.8V VDD. The output impedance control allows the user to adjust the drive strength to adapt to a wide range of loads and transmission lines.

Clocking

The DDRII SRAM has two sets of input clocks, namely the K, K clocks and the C, C clocks. In addition, the DDRII has an output “echo” clock, CQ, CQ.

The K and K clocks are the primary device input clocks. The K clock is used to clock in the control signals LD, R/W and BWx or NWx , the address, and the first word of the data burst during a write operation.

Functional Block Diagram

WRITE/READ DECODE SENSE AMPS OUTPUT REG

OUTPUT SELECT

DATA REG

Note2 SA SA0

ADD REG

Note2

LD R/W BWx

Note3

CTRL LOGIC

Note 1

WRITE DRIVER
18M MEMORY

ARRAY

Note1

Note4

Note1 DQ

SELECT OUTPUT CONTROL

Notes
6112 drw 16
1 Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36
2 Represents 20 address signal lines for x8 and x9, 19 address signal lines for x18, and 18 address signal lines for x36. 3 Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a “nibble write” and there are 2
signal lines.
4 Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36.
Ordering Information

IDT 71P71XXX

Device Type

Power Speed

BQ Package
165 Fine Pitch Ball Grid Array fBGA
333 300 250 Clock Frequency in MegaHertz 200 167

IDT71P71204 2M x 8 DDR II SRAM Burst of 2 IDT71P71104 2M x 9 DDR II SRAM Burst of 2 IDT71P71804 1M x 18 DDR II SRAM Burst of 2 IDT71P71604 512K x 36 DDR II SRAM Burst of 2
6112 drw 15

CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES 800-345-7015 or 408-727-6116 fax 408-492-8674
for Tech Support 800-544-7726
“QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “

IDT71P71204 2M x 8-Bit , 71P71104 2M x 9-Bit , 71P71804 1M x 18 x -Bit 71P71604 512K x 36-Bit

Advance Information
18 Mb DDR II SRAM Burst of 2

Commercial Temperature Range

DATE 05/31/04

PAGES DESCRIPTION 1-23 Initial Advance Information Data Sheet Release

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT71P71604S200BQ8 Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT71P71604S200BQ8 637322