IDT5V995PFGI
IDT5V995PFGI Datasheet
IDT5V995 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II
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IDT5V995PFGI |
IDT5V995PFGI (pdf) |
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IDT5V995PFGI8 |
IDT5V995PFGI8 |
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| IDT5V995 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II INDUSTRIAL TEMPERATURE RANGE IDT5V995 FEATURES: • Ref input is 5V tolerant • 4 pairs of programmable skew outputs • Low skew 185ps same pair, 250ps all outputs • Selectable positive or negative edge synchronization: Excellent for DSP applications • Synchronous output enable • Input frequency 2MHz to 200MHz • Output frequency 6MHz to 200MHz • 3-level inputs for skew and PLL range control • 3-level inputs for feedback divide selection multiply / divide ratios of 1-6, 8, 10, 12 / 2, 4 • PLL bypass for DC testing • External feedback, internal loop filter • 12mA balanced drive outputs • Low Jitter <100ps cycle-to-cycle • Power-down mode • Lock indicator • Available in TQFP package DESCRIPTION: The IDT5V995 is a high fanout 3.3V PLL based clock driver intended for high performance computing and data-communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The IDT5V995 has eight programmable skew outputs in four banks of Skew is controlled by 3-level input signals that may be hardwired to appropriate HIGH-MID-LOW levels. The feedback input allows divide-by-functionality from 1 to 12 through the use of the DS[1:0] inputs. This provides the user with frequency multiplication from 1 to 12 without using divided outputs for feedback. When the sOE pin is held low, all the outputs are synchronously enabled. However, if sOE is held high, all the outputs except 2Q0 and 2Q1 are synchronously disabled. The LOCK output asserts to indicate when Phase Lock has been achieved. Furthermore, when PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When PE is held low, all the outputs are synchronized with the negative edge of REF. The IDT5V995 has LVTTL outputs with 12mA balanced drive outputs. FUNCTIONAL BLOCK DIAGRAM PE TEST FS LOCK sOE REF FB DS1:0 1F1:0 3 Skew S e le c t 1Q0 1Q1 2F1:0 3 Skew S e le c t 2Q0 2Q1 3F1:0 3 Skew S e le c t 3Q0 3Q1 4F1:0 3 Skew S e le c t 4Q0 4Q1 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE 1 c 2004 Integrated Device Technology, Inc. February 20, 2009 DSC 5851/8 IDT5V995 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION 4F0 3F1 3F0 FS VDD REF GND TEST 2F1 2F0 1F1 4F1 sOE PD PE VDDQ 4Q1 4Q0 GND 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 1F0 DS1 DS0 LOCK VDDQ 1Q0 1Q1 GND ORDERING INFORMATION Device Type Package X Package INDUSTRIAL TEMPERATURE RANGE -40°C to +85°C Industrial PF PFG Thin Quad Flat Pack TQFP - Green 5V995 3.3V Programmable Skew PLL Clock Driver TurboClock II CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support: |
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