IDT5V994JGI

IDT5V994JGI Datasheet

IDT5V994 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS

Part	Datasheet
IDT5V994JGI	IDT5V994JGI (pdf)

Related Parts	Information
IDT5V994PFGI	IDT5V994PFGI
IDT5V994PFGI8	IDT5V994PFGI8
IDT5V994JGI8	IDT5V994JGI8

PDF Datasheet Preview
IDT5V994 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS INDUSTRIAL TEMPERATURE RANGE IDT5V994 FEATURES: • Ref input is 5V tolerant • 4 pairs of programmable skew outputs • Low skew 200ps same pair, 250ps all outputs • Selectable positive or negative edge synchronization: Excellent for DSP applications • Synchronous output enable • Input frequency 17.5MHz to 133MHz • Output frequency 17.5MHz to 133MHz • 2x, 4x, 1/2, and 1/4 outputs of VCO frequency • 3-level inputs for skew control • PLL bypass for DC testing • External feedback, internal loop filter • 12mA balanced drive outputs • Low Jitter <200ps cycle-to-cycle • Available in PLCC and TQFP packages The IDT5V994 is a high fanout 3.3V PLL based clock driver intended for high performance computing and data-communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The IDT5V994 has eight programmable skew outputs in four banks of Skew is controlled by 3-level input signals that may be hardwired to appropriate HIGH-MID-LOW levels. When the sOE pin is held low, all the outputs are synchronously enabled. However, if sOE is held high, all the outputs except 3Q0 and 3Q1 are synchronously disabled. Furthermore, when the PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When PE is held low, all the outputs are synchronized with the negative edge of REF. The IDT5V994 has LVTTL outputs with 12mA balanced drive outputs. FUNCTIONAL BLOCK DIAGRAM PE TEST REF PLL FB The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE c 2006 Integrated Device Technology, Inc. Skew Select 33 1F1:0 Skew Select 33 2F1:0 Skew Select 33 3F1:0 Skew Select 33 4F1:0 1Q0 1Q1 2Q0 2Q1 3Q0 3Q1 4Q0 4Q1 MARCH 2006 DSC 5828/6 IDT5V994 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS PIN CONFIGURATIONS INDUSTRIAL TEMPERATURE RANGE 3F0 VDD REF GND TEST 2F1 3F0 VDD REF GND TEST 2F1 2F0 3F1 4F0 4F1 PE VDDQ 4Q1 4Q0 GND 4 3 2 1 32 31 30 14 15 16 17 18 19 20 2F0 sOE 1F1 1F0 VDDQ 1Q0 1Q1 GND 3F1 4F0 4F1 PE VDDQ 4Q1 4Q0 GND 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 ORDERING INFORMATION Device Type Package X Package INDUSTRIAL TEMPERATURE RANGE -40°C to +85°C Industrial J JG PF PFG 32-pin PLCC 32-pin PLCC - Green 32-pin TQFP 32-pin TQFP - Green 5V994 3.3V Programmable Skew PLL Clock Driver TurboClock Plus CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support:

PDF Datasheet Preview

IDT5V994 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS

INDUSTRIAL TEMPERATURE RANGE

IDT5V994

FEATURES:
• Ref input is 5V tolerant
• 4 pairs of programmable skew outputs
• Low skew 200ps same pair, 250ps all outputs
• Selectable positive or negative edge synchronization:

Excellent for DSP applications
• Synchronous output enable
• Input frequency 17.5MHz to 133MHz
• Output frequency 17.5MHz to 133MHz
• 2x, 4x, 1/2, and 1/4 outputs of VCO frequency
• 3-level inputs for skew control
• PLL bypass for DC testing
• External feedback, internal loop filter
• 12mA balanced drive outputs
• Low Jitter <200ps cycle-to-cycle
• Available in PLCC and TQFP packages

The IDT5V994 is a high fanout 3.3V PLL based clock driver intended for high performance computing and data-communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The IDT5V994 has eight programmable skew outputs in four banks of Skew is controlled by 3-level input signals that may be hardwired to appropriate HIGH-MID-LOW levels.

When the sOE pin is held low, all the outputs are synchronously enabled. However, if sOE is held high, all the outputs except 3Q0 and 3Q1 are synchronously disabled.

Furthermore, when the PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When PE is held low, all the outputs are synchronized with the negative edge of REF. The IDT5V994 has LVTTL outputs with 12mA balanced drive outputs.

FUNCTIONAL BLOCK DIAGRAM

PE TEST REF

PLL FB

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE
c 2006 Integrated Device Technology, Inc.

Skew Select 33
1F1:0

Skew Select 33
2F1:0

Skew Select 33
3F1:0

Skew Select 33
4F1:0
1Q0 1Q1
2Q0 2Q1
3Q0 3Q1
4Q0 4Q1

MARCH 2006

DSC 5828/6

IDT5V994 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS

PIN CONFIGURATIONS

INDUSTRIAL TEMPERATURE RANGE
3F0 VDD REF GND TEST 2F1 3F0 VDD REF GND TEST 2F1 2F0
3F1 4F0 4F1 PE VDDQ 4Q1 4Q0 GND
4 3 2 1 32 31 30
14 15 16 17 18 19 20
2F0 sOE 1F1 1F0 VDDQ 1Q0 1Q1 GND
3F1 4F0 4F1 PE VDDQ 4Q1 4Q0 GND
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
ORDERING INFORMATION

Device Type Package

X Package

INDUSTRIAL TEMPERATURE RANGE
-40°C to +85°C Industrial

J JG PF PFG
32-pin PLCC 32-pin PLCC - Green 32-pin TQFP 32-pin TQFP - Green
5V994 3.3V Programmable Skew PLL Clock Driver TurboClock Plus

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775
for Tech Support:

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT5V994JGI Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT5V994JGI 637305