IDT5T93GL161PFGI8

IDT5T93GL161PFGI8 Datasheet

IDT5T93GL161

Part	Datasheet
IDT5T93GL161PFGI8	IDT5T93GL161PFGI8 (pdf)

Related Parts	Information
5T93GL161PFGI	5T93GL161PFGI

PDF Datasheet Preview
2.5V LVDS, 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER II IDT5T93GL161 The IDT5T93GL161 2.5V differential clock buffer is a user-selectable differential input to sixteen LVDS outputs. The fanout from a differential input to sixteen LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The IDT5T93GL161 can act as a translator from a differential HSTL, eHSTL, LVEPECL 2.5V , LVPECL 3.3V , CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for a glitchless change-over from a primary clock source to a secondary clock source. Selectable inputs are controlled by SEL. During the switchover, the output will disable LOW for up to three clock cycles of the previously-selected input clock. The outputs will remain LOW for up to three clock cycles of the newly-selected clock, after which the outputs will start from the newly-selected input. A FSEL pin has been implemented to control the switchover in cases where a clock source is absent or is driven to DC levels below the minimum specifications. The IDT5T93GL161 outputs can be asynchronously enabled/disabled. When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise. • Guaranteed low skew <75ps maximum • Very low duty cycle distortion <100ps maximum • High speed propagation delay <2.2ns maximum • Up to 450MHz operation • Selectable inputs • Hot insertable and over-voltage tolerant inputs • 3.3V/2.5V LVTTL, HSTL, eHSTL, LVEPECL 2.5V , LVPECL 3.3V , CML or LVDS input interface • Selectable differential inputs to sixteen LVDS outputs • Power-down mode • At power-up, FSEL should be LOW • 2.5V VDD • -40°C to 85°C ambient operating temperature • Available in TQFP package • Clock distribution Pin Assignment FSEL PD GND VDD Q13 Q14 Q15 Q16 Q16 VDD GND SEL G1 GND VDD Q1 Q2 Q3 Q4 VDD A1 GND 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 IDT5T93GL161 64-Lead TQFP E-Pad 8 10mm x 10mm x 1.0mm package body 41 Y package Top View 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 G2 GND VDD Q12 Q11 Q10 Q10 Q9 VDD A2 GND GL GND VDD Q5 Q6 Q7 Q8 nc VDD GND IDT LVDS GLITCHLESS CLOCK BUFFER TERABUFFER II IDT5T93GL161 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER II Block Diagram GL G1 A2 SEL FSEL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL Ordering Information Table Ordering Information Device Type Package X Process -40 C to +85 C Industrial PF PFG Thin Quad Flat Pack TQFP - Green 5T93GL161 2.5V LVDS 1:16 Glitchless Clock Buffer Terabuffer II IDT LVDS GLITCHLESS CLOCK BUFFER TERABUFFER II IDT5T93GL161 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER II T3A T3B A 4 16 17 Description of Change Added Gate Control Output Table. Added Selection Table. Added Package Outline. Added Package Dimensions. Updated datasheet format. Date 9/12/08 IDT LVDS GLITCHLESS CLOCK BUFFER TERABUFFER II IDT5T93GL161 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER II Contact Information: Sales 800-345-7015 inside USA +408-284-8200 outside USA Fax 408-284-2775 Technical Support +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 inside USA +408-284-8200 outside USA 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

PDF Datasheet Preview

2.5V LVDS, 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER II

IDT5T93GL161

The IDT5T93GL161 2.5V differential clock buffer is a user-selectable differential input to sixteen LVDS outputs. The fanout from a differential input to sixteen LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The IDT5T93GL161 can act as a translator from a differential HSTL, eHSTL, LVEPECL 2.5V , LVPECL 3.3V , CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for a glitchless change-over from a primary clock source to a secondary clock source. Selectable inputs are controlled by SEL. During the switchover, the output will disable LOW for up to three clock cycles of the previously-selected input clock. The outputs will remain LOW for up to three clock cycles of the newly-selected clock, after which the outputs will start from the newly-selected input. A FSEL pin has been implemented to control the switchover in cases where a clock source is absent or is driven to DC levels below the minimum specifications.

The IDT5T93GL161 outputs can be asynchronously enabled/disabled. When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise.
• Guaranteed low skew <75ps maximum
• Very low duty cycle distortion <100ps maximum
• High speed propagation delay <2.2ns maximum
• Up to 450MHz operation
• Selectable inputs
• Hot insertable and over-voltage tolerant inputs
• 3.3V/2.5V LVTTL, HSTL, eHSTL, LVEPECL 2.5V , LVPECL
3.3V , CML or LVDS input interface
• Selectable differential inputs to sixteen LVDS outputs
• Power-down mode
• At power-up, FSEL should be LOW
• 2.5V VDD
• -40°C to 85°C ambient operating temperature
• Available in TQFP package
• Clock distribution

Pin Assignment

FSEL PD

GND VDD Q13 Q14 Q15 Q16

Q16 VDD GND SEL

G1 GND

VDD Q1 Q2 Q3 Q4 VDD A1 GND
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

IDT5T93GL161
64-Lead TQFP E-Pad
8 10mm x 10mm x 1.0mm package body 41

Y package

Top View
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

G2 GND VDD Q12 Q11 Q10

Q10 Q9 VDD A2 GND

GL GND

VDD Q5 Q6 Q7 Q8
nc VDD GND

IDT LVDS GLITCHLESS CLOCK BUFFER TERABUFFER II

IDT5T93GL161 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER II

Block Diagram

GL G1

A2 SEL FSEL

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL
Ordering Information
Table Ordering Information

Device Type Package

X Process
-40 C to +85 C Industrial

PF PFG

Thin Quad Flat Pack TQFP - Green
5T93GL161 2.5V LVDS 1:16 Glitchless Clock Buffer Terabuffer II

IDT LVDS GLITCHLESS CLOCK BUFFER TERABUFFER II

IDT5T93GL161 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER II

T3A T3B A
4 16 17

Description of Change

Added Gate Control Output Table. Added Selection Table. Added Package Outline. Added Package Dimensions. Updated datasheet format.

Date 9/12/08

IDT LVDS GLITCHLESS CLOCK BUFFER TERABUFFER II

IDT5T93GL161 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER II

Contact Information:

Sales
800-345-7015 inside USA +408-284-8200 outside USA Fax 408-284-2775

Technical Support
+480-763-2056

Corporate Headquarters

Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 inside USA +408-284-8200 outside USA
2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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Datasheet ID: IDT5T93GL161PFGI8 637281