5T93GL101PFGI

5T93GL101PFGI Datasheet

IDT5T93GL101 2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER II

Part	Datasheet
5T93GL101PFGI	5T93GL101PFGI (pdf)

Related Parts	Information
5T93GL101PFGI8	5T93GL101PFGI8

PDF Datasheet Preview
IDT5T93GL101 2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER II INDUSTRIAL TEMPERATURE RANGE 2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER II IDT5T93GL101 FEATURES: • Guaranteed Low Skew < 75ps max • Very low duty cycle distortion < 100ps max • High speed propagation delay < 2.2ns max • Up to 450MHz operation • Selectable inputs • Hot insertable and over-voltage tolerant inputs • 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL 2.5V , LVPECL 3.3V , CML, or LVDS input interface • Selectable differential inputs to ten LVDS outputs • Power-down mode • 2.5V VDD • Available in TQFP package APPLICATIONS: • Clock distribution DESCRIPTION: The IDT5T93GL101 2.5V differential clock buffer is a user-selectable differential input to ten LVDS outputs The fanout from a differential input to ten LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The IDT5T93GL101 can act as a translator from a differential HSTL, eHSTL, LVEPECL 2.5V , LVPECL 3.3V , CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for a glitchless change-over from a primary clock source to a secondary clock source. Selectable inputs are controlled by SEL. During the switchover, the output will disable low for up to three clock cycles of the previously-selected input clock. The outputs will remain low for up to three clock cycles of the newlyselected clock, after which the outputs will start from the newly-selected input. A FSEL pin has been implemented to control the switchover in cases where a clock source is absent or is driven to DC levels below the minimum specifications. The IDT5T93GL101 outputs can be asynchronously enabled/disabled. When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise. FUNCTIONAL BLOCK DIAGRAM OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL SEL FSEL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE 2007 Integrated Device Technology, Inc. OUTPUT CONTROL OUTPUT CONTROL JANUARY 2007 DSC-6741/5 IDT5T93GL101 2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER II PIN CONFIGURATION INDUSTRIAL TEMPERATURE RANGE SEL VDD GND Q10 Q9 Q8 VDD FSEL ORDERING INFORMATION Device Type Package Process INDUSTRIAL TEMPERATURE RANGE -40°C to +85°C Industrial PF PFG Thin Quad Flat Pack TQFP - Green 5T93GL101 2.5V LVDS 1:10 Glitchless Clock Buffer Terabuffer II CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support:

PDF Datasheet Preview

IDT5T93GL101 2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER II

INDUSTRIAL TEMPERATURE RANGE
2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER II

IDT5T93GL101

FEATURES:
• Guaranteed Low Skew < 75ps max
• Very low duty cycle distortion < 100ps max
• High speed propagation delay < 2.2ns max
• Up to 450MHz operation
• Selectable inputs
• Hot insertable and over-voltage tolerant inputs
• 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL 2.5V , LVPECL 3.3V ,

CML, or LVDS input interface
• Selectable differential inputs to ten LVDS outputs
• Power-down mode
• 2.5V VDD
• Available in TQFP package

APPLICATIONS:
• Clock distribution

DESCRIPTION:

The IDT5T93GL101 2.5V differential clock buffer is a user-selectable differential input to ten LVDS outputs The fanout from a differential input to ten LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The IDT5T93GL101 can act as a translator from a differential HSTL, eHSTL, LVEPECL 2.5V , LVPECL 3.3V , CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for a glitchless change-over from a primary clock source to a secondary clock source. Selectable inputs are controlled by SEL. During the switchover, the output will disable low for up to three clock cycles of the previously-selected input clock. The outputs will remain low for up to three clock cycles of the newlyselected clock, after which the outputs will start from the newly-selected input. A FSEL pin has been implemented to control the switchover in cases where a clock source is absent or is driven to DC levels below the minimum specifications.

The IDT5T93GL101 outputs can be asynchronously enabled/disabled. When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise.

FUNCTIONAL BLOCK DIAGRAM

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

SEL FSEL

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE
2007 Integrated Device Technology, Inc.

OUTPUT CONTROL

OUTPUT CONTROL

JANUARY 2007

DSC-6741/5

IDT5T93GL101 2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER II

PIN CONFIGURATION

INDUSTRIAL TEMPERATURE RANGE

SEL VDD GND Q10 Q9 Q8 VDD FSEL
ORDERING INFORMATION

Device Type Package Process

INDUSTRIAL TEMPERATURE RANGE
-40°C to +85°C Industrial

PF PFG

Thin Quad Flat Pack TQFP - Green
5T93GL101 2.5V LVDS 1:10 Glitchless Clock Buffer Terabuffer II

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775
for Tech Support:

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 5T93GL101PFGI Datasheet file may be downloaded here without warranties.

Datasheet ID: 5T93GL101PFGI 637279